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公开(公告)号：US10177794B1
公开(公告)日：2019-01-08
申请号：US15372221
申请日：2016-12-07
Applicant: Xilinx, Inc.
Inventor： Kumar Rahul , Amarnath Perla , Santosh Yachareni
Abstract: An integrated circuit (IC) includes an encoder configured to receive input data including a plurality of data bits. The encoder includes a parity computation matrix circuit configured to arrange the data bits according to a matrix format to generate a parity computation matrix. A parity computation circuit is configured to compute a plurality of parity computation row terms corresponding to rows of the parity computation matrix respectively, compute a plurality of parity computation column terms corresponding to columns of the parity computation matrix respectively, and compute parity bits using the parity computation row terms and parity computation column terms. Write data including the data bits and the parity bits are provided to a write circuit. The write circuit writes the write data to a memory cell array in a memory.
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公开(公告)号：US12190994B2
公开(公告)日：2025-01-07
申请号：US18090574
申请日：2022-12-29
Applicant: XILINX, INC.
Inventor： Kumar Rahul , Santosh Yachareni , Mahendrakumar Gunasekaran , Mohammad Anees
Abstract: An integrated circuitry (IC) device for a memory device includes driver circuitry, selection circuitry, clock generation circuitry, and self-time path circuitry. The driver circuitry generates a plurality of driver circuitry outputs. The selection circuitry selects one of the plurality of driver circuitry outputs based on a plurality of enable signals. The clock generation circuitry receives the selected one of the plurality of driver circuitry outputs from the selection circuitry, and generates a clock signal based on at least the selected one of the plurality of driver circuitry outputs from the selection circuitry. The self-time path circuitry of a memory receives the clock signal and generates a reset signal based on the clock signal. The plurality of driver circuitry outputs and the clock signal are based on the reset signal, and the self-time path circuitry corresponds to one or more columns of a memory bank.
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公开(公告)号：US12045469B2
公开(公告)日：2024-07-23
申请号：US18082223
申请日：2022-12-15
Applicant: XILINX, INC.
Inventor： Kumar Rahul , John J. Wuu , Santosh Yachareni , Nui Chong , Cheang Whang Chang
CPC classification number: G06F3/0619 , G06F3/0629 , G06F3/0673
Abstract: A memory device is disclosed herein that leverages high ratio column MUXES to improve SEU resistance. The memory device may be utilized in an integrated circuit die and chip packages having the same. In one example, as semiconductor memory device is provided that includes first and second arrays of semiconductor memory cells, a plurality of sense amplifiers configured to read data states from the first and second arrays of memory cells, and a first plurality of high ratio MUXES connecting the first and second arrays of memory cells to the plurality of sense amplifiers.
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公开(公告)号：US10169264B1
公开(公告)日：2019-01-01
申请号：US15639752
申请日：2017-06-30
Applicant: Xilinx, Inc.
Inventor： Michelle E. Zeng , Subodh Kumar , Uma Durairajan , Weiguang Lu , Karthy Rajasekharan , Kumar Rahul
IPC: G06F13/16 , H03K19/177 , G06F3/06 , G06F13/40 , G11C7/10 , G01R31/3185
Abstract: In an example, a memory circuit in a programmable integrated circuit (IC) includes: a control port and a clock port; a configurable random access memory (RAM) having a control input and a clock input; input multiplexer logic coupled to the control input and the clock input; and a state machine coupled to the input multiplexer logic and configuration logic of the programmable IC, the state machine configured to: in response to being enabled by the configuration logic, control the input multiplexer logic to switch a connection of the control input from the control port to the state machine and, subsequently, switch a connection of the clock input from the clock port to a configuration clock source; and in response to being disabled by the configuration logic, control the input multiplexer logic to switch the connection of the clock input from the configuration clock source to the clock port and, subsequently, switch the connection of the control input from the state machine to the control port.
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Patent Agency Ranking
公开(公告)号：US12212337B2
公开(公告)日：2025-01-28
申请号：US18128943
申请日：2023-03-30
Applicant: XILINX, INC. , Advanced Micro Devices, Inc.
Inventor： Kumar Rahul , John J. Wuu , Santosh Yachareni
Abstract: An integrated circuit (IC) device includes an error correction code (ECC) encoder circuitry configured to receive input data, determine min-terms in a Hamming matrix (H-Matrix) corresponding to the input data, and generate ECC data based on the min-terms and an output codeword based on the ECC data, and an error correction circuitry configured to generate a corrected output codeword based on the output codeword.
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公开(公告)号：US11088678B1
公开(公告)日：2021-08-10
申请号：US16788262
申请日：2020-02-11
Applicant: XILINX, INC.
Inventor： Kumar Rahul , Mohammad Anees , Mahendrakumar Gunasekaran
IPC: H03K3/356 , H03K3/3562 , H03K19/0185 , H03K3/037 , H03K3/0233
Abstract: Examples described herein generally relate to devices that include a pulsed flip-flop capable of being implemented across multiple voltage domains. In an example, a device includes a pulsed flip-flop. The pulsed flip-flop includes a master circuit and a slave circuit sequentially connected to the master circuit. The master circuit includes a pre-charge input circuit and a first latch. A first node is connected between the pre-charge input circuit and the first latch. The slave circuit includes a resolving circuit and a second latch. The first node is connected to an input node of the resolving circuit. A second node is connected between the resolving circuit and the second latch. The resolving circuit is configured to selectively (i) pull up or pull down a voltage of the second node and (ii) be disabled.
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公开(公告)号：US10725841B1
公开(公告)日：2020-07-28
申请号：US15844919
申请日：2017-12-18
Applicant: Xilinx, Inc.
Inventor： Kumar Rahul , Santosh Yachareni
Abstract: An integrated circuit (IC) includes an encoder circuit configured to receive input data including a plurality of data bits. A plurality of parity computation equations for a single error correct double error detect adjacent double error correct adjacent triple error detect (SECDEDADECADTED) Hamming code is received. A plurality of parity bits are computed using the plurality of parity computation equations. Write data including the data bits and the parity bits are provided to a write circuit. The write circuit writes the write data to a memory.
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公开(公告)号：US10979034B1
公开(公告)日：2021-04-13
申请号：US16012557
申请日：2018-06-19
Applicant: Xilinx, Inc.
Inventor： Kumar Rahul , Santosh Yachareni , Jitendra Kumar Yadav , Md Nadeem Iqbal , Teja Masina , Sourabh Swarnkar , Suresh Babu Kotha
IPC: H03K3/3562 , H03K3/012 , H03K3/037 , H03K19/0185 , H03K19/00
Abstract: A circuit includes a master latch circuit and a slave latch circuit. The master latch circuit is configured to receive an input data signal associated with an input data voltage domain and generate a first output data signal associated with an output data voltage domain different from the input data voltage domain. The slave latch circuit is configured to receive, from the master latch circuit, the first output data signal and generate a second output data associated with the output data voltage domain.
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公开(公告)号：US10673464B1
公开(公告)日：2020-06-02
申请号：US16106725
申请日：2018-08-21
Applicant: Xilinx, Inc.
Inventor： Kumar Rahul , Santosh Yachareni
Abstract: An apparatus includes an encoder circuit block configured to receive input data. The encoder circuit block is configured to generate a plurality of parity bits from the input data and order the input data and the plurality of parity bits to generate encoded data. The encoder circuit block is configured to generate each of the plurality of parity bits based upon selected bits of the input data and orders the input data and the plurality of parity bits so that a decoder circuit block configured to decode the encoded data is able to perform operations including, at least in part, detecting a no bit error, detecting and correcting a single bit error, detecting a double bit error, detecting and correcting an adjacent double bit error, and detecting an adjacent triple bit error. The operations are independent of a number of memory banks used to store the encoded data. The decoder circuit block may also correct an adjacent triple bit error.
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