公开(公告)号：US10979034B1

公开(公告)日：2021-04-13

申请号：US16012557

申请日：2018-06-19

Applicant: Xilinx, Inc.

Inventor： Kumar Rahul ,  Santosh Yachareni ,  Jitendra Kumar Yadav ,  Md Nadeem Iqbal ,  Teja Masina ,  Sourabh Swarnkar ,  Suresh Babu Kotha

IPC: H03K3/3562 ,  H03K3/012 ,  H03K3/037 ,  H03K19/0185 ,  H03K19/00

Abstract: A circuit includes a master latch circuit and a slave latch circuit. The master latch circuit is configured to receive an input data signal associated with an input data voltage domain and generate a first output data signal associated with an output data voltage domain different from the input data voltage domain. The slave latch circuit is configured to receive, from the master latch circuit, the first output data signal and generate a second output data associated with the output data voltage domain.