公开(公告)号：US20230023614A1

公开(公告)日：2023-01-26

申请号：US17385313

申请日：2021-07-26

Applicant: Xilinx, Inc.

Inventor： Michael Tsivyan ,  Shidong Zhou ,  Karthy Rajasekharan ,  Weiguang Lu ,  Jing Jing Chen ,  Mehul Vashi

IPC: G11C11/419 ,  G11C11/418 ,  H01L27/11

Abstract: First and second sensing circuits are coupled to first and second data lines, respectively, and sense levels of current leakage or a memory cell state on the first and second data lines. First and second keeper circuits are coupled to the first and second data lines, respectively, and drive the first and second data lines by a voltage supply through biased transistors. First and second leakage latches are coupled to receive and latch state of signals output from the first and second sensing circuits, respectively. A control circuit is coupled to the first leakage latch, second leakage latch, and outputs of the first and second sensing circuits. The control circuit is configured to select either the signal output from the first sensing circuit or the signal output from the second sensing circuit in response to states of the first and second leakage latches.

公开(公告)号：US11386009B2

公开(公告)日：2022-07-12

申请号：US16670570

申请日：2019-10-31

Applicant: XILINX, INC.

Inventor： David P. Schultz ,  Weiguang Lu ,  Karthy Rajasekharan ,  Shidong Zhou ,  Michael Tsivyan ,  Jing Jing Chen ,  Sourabh Goyal

IPC: G06F12/0855 ,  G06F9/30 ,  G06F12/06 ,  G06F12/0895 ,  G06F13/16

Abstract: An example configuration system for a programmable device includes: a configuration memory read/write unit configured to receive configuration data for storage in a configuration memory of the programmable device, the configuration memory comprising a plurality of frames; a plurality of configuration memory read/write controllers coupled to the configuration memory read/write unit; a plurality of fabric sub-regions (FSRs) respectively coupled to the plurality of configuration memory read/write controllers, each FSR including a pipeline of memory cells of the configuration memory disposed between buffers and a configuration memory read/write pipeline unit coupled between the pipeline and a next one of the plurality of FSRs.

公开(公告)号：US10566050B1

公开(公告)日：2020-02-18

申请号：US15927797

申请日：2018-03-21

Applicant: Xilinx, Inc.

Inventor： Shidong Zhou ,  Nui Chong ,  Jing Jing Chen

IPC: G11C11/00 ,  G11C11/419 ,  G11C11/412 ,  G11C11/418

Abstract: Embodiments herein describe a memory cell (e.g., a SRAM memory cell) that includes power selection logic for disconnecting storage inverters from a reference voltage source when writing data into the cell. In one embodiment, the memory cells may be disposed long distances (e.g., more than 100 microns) from the data drivers in the integrated circuit which can result in the data lines having large RC time constants. In one embodiment, disconnecting the memory cells from a power supply may counter (or mitigate) the large RC time constants of the data lines.

公开(公告)号：US12148464B2

公开(公告)日：2024-11-19

申请号：US17385313

申请日：2021-07-26

Applicant: Xilinx, Inc.

Inventor： Michael Tsivyan ,  Shidong Zhou ,  Karthy Rajasekharan ,  Weiguang Lu ,  Jing Jing Chen ,  Mehul Vashi

IPC: G11C11/419 ,  G11C11/418 ,  H10B10/00

Abstract: First and second sensing circuits are coupled to first and second data lines, respectively, and sense levels of current leakage or a memory cell state on the first and second data lines. First and second keeper circuits are coupled to the first and second data lines, respectively, and drive the first and second data lines by a voltage supply through biased transistors. First and second leakage latches are coupled to receive and latch state of signals output from the first and second sensing circuits, respectively. A control circuit is coupled to the first leakage latch, second leakage latch, and outputs of the first and second sensing circuits. The control circuit is configured to select either the signal output from the first sensing circuit or the signal output from the second sensing circuit in response to states of the first and second leakage latches.

公开(公告)号：US10411710B1

公开(公告)日：2019-09-10

申请号：US16211149

申请日：2018-12-05

Applicant: Xilinx, Inc.

Inventor： Shidong Zhou ,  Sree RKC Saraswatula ,  Jing Jing Chen ,  Teja Masina ,  Narendra Kumar Pulipati ,  Santosh Yachareni

IPC: H03K19/177

Abstract: An example read address generation circuit for a static random access memory (SRAM) cell includes an operational amplifier having a non-inverting input coupled to a reference voltage, a memory emulation circuit having an output coupled to an inverting input of the operational amplifier and a control input coupled to an output of the operational amplifier, and a multiplexer having a first input coupled to receive a constant read voltage, a second input coupled to the output of the operational amplifier, and an output coupled to supply a read address voltage to the SRAM cell.

公开(公告)号：US10396799B1

公开(公告)日：2019-08-27

申请号：US15839462

申请日：2017-12-12

Applicant: Xilinx, Inc.

Inventor： Vishwak R Manda ,  Sree RKC Saraswatula ,  Santosh Yachareni ,  Shidong Zhou ,  Jing Jing Chen ,  Michael Tsivyan

IPC: H03K19/177 ,  H03K19/00 ,  H03K19/0185

Abstract: A circuit for accessing memory elements in an integrated circuit device is described. The circuit comprises a first plurality of memory elements; first line drivers, each of the first line drivers configured to provide a signal to a memory element of the first plurality of memory elements; first line driver buffers configured to control the signals provided by the first line drivers to the first plurality of memory elements; a second plurality of memory elements; second line drivers, each of the second line drivers configured to provide a signal to a memory element of the second plurality of memory elements; second line driver buffers configured to control the signals provided by the second line drivers to the second plurality of memory elements; and wherein one or both of the first line driver buffers and the second line driver buffers are configured to be selectively disabled.

公开(公告)号：US09721649B1

公开(公告)日：2017-08-01

申请号：US15237395

申请日：2016-08-15

Applicant: Xilinx, Inc.

Inventor： Shidong Zhou ,  Jing Jing Chen

IPC: G11C7/00 ,  G11C11/419

CPC classification number: G11C11/419 ,  G11C7/04

Abstract: A circuit for implementing a write operation of a memory is described. The circuit comprises a data line buffer coupled to a data line and an inverted data line for writing data; a plurality of memory elements, each memory element having a first node coupled to the data line and a second node coupled to the inverted data line; and a write assist circuit having a first node coupled to data line and a second node coupled to the inverted data line, wherein the write assist circuit comprises a pair of pull-down transistors comprising first pull-down transistor coupled to the first node of an amplifier portion and a second pull-down transistor coupled to a second node of the amplifier portion, and a pair of pull-up transistors comprising a first pull-up transistor coupled to the first node of the amplifier portion and a second pull-up transistor coupled to the second node of the amplifier portion. A method of implementing a write operation of a memory of a memory is also described.