公开(公告)号：US20190333892A1

公开(公告)日：2019-10-31

申请号：US15967109

申请日：2018-04-30

Applicant: Xilinx, Inc.

Inventor： Brian C. Gaide ,  Matthew H. Klein

IPC: H01L25/065 ,  H01L25/00 ,  H01L21/66 ,  H01L23/535

Abstract: Examples herein describe techniques for forming 3D stacked devices which include a redundant logical layer. The 3D stacked devices include a plurality of semiconductor chips stacked in a vertical direction such that each chip is bonded to a chip above, below, or both in the stack. In one embodiment, each chip is the same—e.g., has the same circuitry arranged in the same configuration in the chip. The 3D stacked device provides a redundant logic layer by dividing the chips into a plurality of slivers which are interconnected by inter-chip bridges. For example, the 3D stacked device may include three stacked chips that are divided into three different slivers where each sliver includes a portion from each of the chips. So long as only one of portions in a sliver is nonfunctional, the inter-chip bridges permit the other portions in the sliver to receive and route data.

公开(公告)号：US09436562B1

公开(公告)日：2016-09-06

申请号：US14171488

申请日：2014-02-03

Applicant: Xilinx, Inc.

Inventor： Matthew H. Klein ,  Chen W. Tseng

IPC: G06F11/00 ,  G06F11/16

CPC classification number: G06F11/1625 ,  G06F11/1004

Abstract: An apparatus relating generally to an error detection system is disclosed. The apparatus includes a first data bus and a second data bus. A first circuit is coupled for communication via the first data bus. A plurality of storage elements are coupled to the first data bus and the second data bus. A second circuit is coupled for communication via the second data bus. The error detection system is coupled to the first data bus and the second data bus. The error detection system is coupled to compare first data on the first data bus with corresponding second data on the second data bus. The error detection system is configured to generate an error signal responsive to mismatch between the first data and the second data.

Abstract translation: 公开了一般涉及错误检测系统的装置。 该装置包括第一数据总线和第二数据总线。 第一电路被耦合用于经由第一数据总线进行通信。 多个存储元件耦合到第一数据总线和第二数据总线。 第二电路被耦合用于经由第二数据总线进行通信。 误差检测系统耦合到第一数据总线和第二数据总线。 错误检测系统被耦合以将第一数据总线上的第一数据与第二数据总线上的对应的第二数据进行比较。 错误检测系统被配置为响应于第一数据和第二数据之间的不匹配而产生误差信号。

公开(公告)号：US09075930B2

公开(公告)日：2015-07-07

申请号：US13673892

申请日：2012-11-09

Applicant: Xilinx, Inc.

Inventor： Subodh Kumar ,  James M. Simkins ,  Thomas H. Strader ,  Matthew H. Klein ,  James E. Ogden ,  Uma Durairajan

IPC: G11C7/10 ,  G06F13/42 ,  H03K19/177 ,  G11C16/26

CPC classification number: G06F13/4234 ,  G11C7/1006 ,  G11C7/1039 ,  G11C7/1069 ,  G11C7/1096 ,  G11C16/26 ,  G11C2207/104 ,  H03K19/17732 ,  H03K19/1776 ,  Y02D10/14 ,  Y02D10/151

Abstract: An embodiment of a memory module is disclosed. This memory module is a configurable hard macro. A portion of this memory module includes a data input multiplexer coupled to select between cascaded data and direct/bused data. Such portion further includes, a memory coupled to receive output from the data input multiplexer for storage therein, and a register input multiplexer coupled to select between read data from the memory and the cascaded data. This memory module further includes: a register coupled to receive output from the register input multiplexer, a latch/register mode multiplexer coupled to select between the read data from the memory and registered data from the register, and a data output multiplexer coupled to select between the cascaded data and output from the latch/register mode multiplexer to provide output data.

Abstract translation: 公开了一种存储器模块的实施例。 该内存模块是可配置的硬宏。 该存储器模块的一部分包括耦合以在级联数据和直接/传输数据之间进行选择的数据输入多路复用器。 该部分还包括：耦合以从数据输入多路复用器接收输出以存储在其中的存储器，以及耦合以在存储器的读取数据和级联数据之间进行选择的寄存器输入多路复用器。 该存储器模块还包括：耦合以接收来自寄存器输入多路复用器的输出的寄存器，耦合以在来自存储器的读取数据和来自寄存器的寄存数据之间进行选择的锁存/寄存器模式多路复用器，以及数据输出多路复用器， 级联数据和从锁存/寄存器模式多路复用器输出以提供输出数据。

公开(公告)号：US20140133246A1

公开(公告)日：2014-05-15

申请号：US13673892

申请日：2012-11-09

Applicant: Xilinx, Inc.

Inventor： Subodh Kumar ,  James M. Simkins ,  Thomas H. Strader ,  Matthew H. Klein ,  James E. Ogden ,  Uma Durairajan

IPC: G11C7/10 ,  G11C8/00

CPC classification number: G06F13/4234 ,  G11C7/1006 ,  G11C7/1039 ,  G11C7/1069 ,  G11C7/1096 ,  G11C16/26 ,  G11C2207/104 ,  H03K19/17732 ,  H03K19/1776 ,  Y02D10/14 ,  Y02D10/151

Abstract: An embodiment of a memory module is disclosed. This memory module is a configurable hard macro. A portion of this memory module includes a data input multiplexer coupled to select between cascaded data and direct/bused data. Such portion further includes, a memory coupled to receive output from the data input multiplexer for storage therein, and a register input multiplexer coupled to select between read data from the memory and the cascaded data. This memory module further includes: a register coupled to receive output from the register input multiplexer, a latch/register mode multiplexer coupled to select between the read data from the memory and registered data from the register, and a data output multiplexer coupled to select between the cascaded data and output from the latch/register mode multiplexer to provide output data.

Abstract translation: 公开了一种存储器模块的实施例。 该内存模块是可配置的硬宏。 该存储器模块的一部分包括耦合以在级联数据和直接/传输数据之间进行选择的数据输入多路复用器。 该部分还包括：耦合以从数据输入多路复用器接收输出以存储在其中的存储器，以及耦合以在存储器的读取数据和级联数据之间进行选择的寄存器输入多路复用器。 该存储器模块还包括：耦合以接收来自寄存器输入多路复用器的输出的寄存器，耦合以在来自存储器的读取数据和来自寄存器的寄存数据之间进行选择的锁存/寄存器模式多路复用器，以及数据输出多路复用器， 级联数据和从锁存/寄存器模式多路复用器输出以提供输出数据。

公开(公告)号：US11386020B1

公开(公告)日：2022-07-12

申请号：US16808054

申请日：2020-03-03

Applicant: XILINX, INC.

Inventor： Matthew H. Klein ,  Goran Hk Bilski ,  Juan Jose Noguera Serra ,  Ismed D. Hartanto ,  Sridhar Subramanian ,  Tim Tuan

IPC: G06F15/17 ,  G06F13/16 ,  G06F9/30 ,  H03K19/1776 ,  G06F7/501 ,  G06F15/173

Abstract: Some examples described herein relate to programmable devices that include a data processing engine (DPE) array that permits shifting of where an application is loaded onto DPEs of the DPE array. In an example, a programmable device includes a DPE array. The DPE array includes DPEs and address index offset logic. Each of the DPEs includes a processor core and a memory mapped switch. The processor core is programmable via one or more memory mapped packets routed through the respective memory mapped switch. The memory mapped switches in the DPE array are coupled together to form a memory mapped interconnect network. The address index offset logic is configurable to selectively modify which DPE in the DPE array is targeted by a respective memory mapped packet routed in the memory mapped interconnect network.

公开(公告)号：US10741524B2

公开(公告)日：2020-08-11

申请号：US15967109

申请日：2018-04-30

Applicant: Xilinx, Inc.

Inventor： Brian C. Gaide ,  Matthew H. Klein

IPC: H01L25/065 ,  H01L23/535 ,  H01L21/66 ,  H01L25/00

Abstract: Examples herein describe techniques for forming 3D stacked devices which include a redundant logical layer. The 3D stacked devices include a plurality of semiconductor chips stacked in a vertical direction such that each chip is bonded to a chip above, below, or both in the stack. In one embodiment, each chip is the same—e.g., has the same circuitry arranged in the same configuration in the chip. The 3D stacked device provides a redundant logic layer by dividing the chips into a plurality of slivers which are interconnected by inter-chip bridges. For example, the 3D stacked device may include three stacked chips that are divided into three different slivers where each sliver includes a portion from each of the chips. So long as only one of portions in a sliver is nonfunctional, the inter-chip bridges permit the other portions in the sliver to receive and route data.

公开(公告)号：US10740523B1

公开(公告)日：2020-08-11

申请号：US16034019

申请日：2018-07-12

Applicant: Xilinx, Inc.

Inventor： Matthew H. Klein

IPC: G06F17/50 ,  G06F30/34 ,  G06F30/373 ,  G06F115/02

Abstract: A programmable logic device includes an integrated circuit die having a programmable fabric region including N identical programmable logic partitions. In some embodiments, N−1 of the identical programmable logic partitions are user-programmable. In addition, and in some cases, one of the identical programmable logic partitions is a spare logic partition. In some embodiments, the integrated circuit die further includes a network-on-a-chip (NOC) including a vertical NOC (VNOC) and a horizontal NOC (HNOC). By way of example, the N identical programmable logic partitions are configured to communicate exclusively through the NOC. In some embodiments, a defective one of the N−1 identical programmable logic partitions is configured for swapping with the spare logic partition.

公开(公告)号：US10402521B1

公开(公告)日：2019-09-03

申请号：US15410597

申请日：2017-01-19

Applicant: Xilinx, Inc.

Inventor： Bart Reynolds ,  Xiaojian Yang ,  Matthew H. Klein

IPC: G06F17/50

Abstract: Methods and apparatus are described for providing and using programmable ICs suitable for meeting the unique desires of large hardware emulation systems. One example method of classifying a programmable IC having impaired circuitry generally includes determining a partitioning of programmable logic resources into two or more groups for classifying the programmable IC, testing the programmable IC to determine at least one location of the impaired circuitry in the programmable logic resources of the programmable IC, and classifying the programmable IC based on the at least one location of the impaired circuitry in relation to the partitioning of the programmable logic resources.

公开(公告)号：US10032682B1

公开(公告)日：2018-07-24

申请号：US15359280

申请日：2016-11-22

Applicant: Xilinx, Inc.

Inventor： Matthew H. Klein ,  Raghunandan Chaware ,  Glenn O'Rourke

IPC: H01L21/66 ,  H01L21/78 ,  H01L21/56 ,  H01L23/00

Abstract: Methods and apparatus are described for creating a multi-die package from a wafer without dicing the wafer into individual dies and reassembling the dies on an interposer. One example method generally includes testing a plurality of IC dies disposed on a wafer; disposing one or more connectivity layers above the plurality of IC dies, the one or more connectivity layers comprising one or more electrical conductors configured to connect together two or more of the plurality of dies in each of one or more groups of the IC dies; dicing the wafer having the one or more connectivity layers disposed above the plurality of dies into sets, each set comprising one or more of the plurality of dies, wherein the dicing is based on the one or more groups having IC dies that passed the testing; and packaging at least a portion of the sets of dies.

公开(公告)号：US09509640B2

公开(公告)日：2016-11-29

申请号：US14561452

申请日：2014-12-05

Applicant: Xilinx, Inc.

Inventor： David F. Taylor ,  Matthew H. Klein ,  Vincent Vendramini

IPC: H04K1/10 ,  G11C7/00 ,  H04L12/861 ,  H03L7/06 ,  G06F5/10 ,  G06F5/06 ,  H03M9/00 ,  G06F5/12

CPC classification number: H04L49/90 ,  G06F5/06 ,  G06F5/10 ,  G06F5/12 ,  G06F2205/126 ,  H03L7/06 ,  H03L7/07 ,  H03M9/00

Abstract: In a method for buffering, a buffer buffers data responsive to read and write clock signals. A flag signal from the buffer is for a fill level thereof. The flag signal is toggled responsive to the data buffered being either above or below a set point for the fill level. A phase of the write clock signal is adjusted to a phase of the read clock signal responsive to the toggling of the flag signal. The write clock signal is used to control latency of the buffer. The adjusting of the phase of the write clock signal includes: generating an override signal responsive to the toggling of the flag signal; and inputting the read clock signal and the override signal to a phase adjuster to controllably adjust the phase of the write clock signal to the phase of the read clock signal during operation.

Abstract translation: 在缓冲方法中，缓冲器缓冲响应于读和写时钟信号的数据。 来自缓冲器的标志信号用于其填充水平。 响应于缓冲的数据高于或低于填充水平的设定点，该标志信号被切换。 响应于标志信号的切换，写时钟信号的相位被调整为读时钟信号的相位。 写时钟信号用于控制缓冲器的延迟。 写时钟信号的相位的调整包括：响应于标志信号的切换产生超控信号; 并将读取的时钟信号和超控信号输入到相位调节器，以在操作期间将写时钟信号的相位可控地调节到读时钟信号的相位。