公开(公告)号：US08866509B1

公开(公告)日：2014-10-21

申请号：US13842664

申请日：2013-03-15

Applicant: Xilinx, Inc.

Inventor： Robert I. Fu ,  Chi M. Nguyen ,  James M. Simkins ,  Brian C. Gaide ,  Brian D. Philoksky

IPC: H03K19/173

CPC classification number: H03K19/173

Abstract: Integrated circuits having groups of flip-flops with the option to ignore control signals are disclosed. For example, an integrated circuit comprises a first group and a second group of flip-flops that share a common reset signal, and a first selection unit for selecting a first output from among the common reset signal and a logical low signal to be sent to the second group of flop-flops. A selection of the logical low signal is for preventing the common reset signal from being applied to the flip-flops in the second group. The integrated circuit may also include a second selection unit for selecting a second output from among the common reset signal and a logical low signal to be sent to the first group of flop-flops. A selection of the logical low signal is for preventing the common reset signal from being applied to the flip-flops in the first group.

Abstract translation: 公开了具有忽略控制信号的选项的具有触发器组的集成电路。 例如，集成电路包括共享公共复位信号的第一组和第二组触发器，以及用于从公共复位信号中选择第一输出的第一选择单元和要发送到的逻辑低电平信号 第二组翻牌。 逻辑低信号的选择用于防止公共复位信号施加到第二组中的触发器。 集成电路还可以包括用于从公共复位信号中选择第二输出的第二选择单元和要发送到第一组触发器的逻辑低信号。 逻辑低信号的选择用于防止公共复位信号施加到第一组中的触发器。

公开(公告)号：US08912829B1

公开(公告)日：2014-12-16

申请号：US13965021

申请日：2013-08-12

Applicant: Xilinx, Inc.

Inventor： James E. Ogden ,  James M. Simkins ,  Uma Durairajan ,  Subodh Kumar

IPC: H03L7/00 ,  H03L7/10 ,  H03K17/22 ,  H02M1/00

CPC classification number: G06F1/24 ,  H02M2001/0032 ,  H03K17/223

Abstract: An integrated circuit and method for using a synchronous reset pulse to reset a circuitry comprising a plurality of clock domains are disclosed. For example, the method of the present disclosure provides a reset signal that is synched to one clock, takes the synchronous signal and resets circuits in a plurality of clock domains. In order to reset a portion of the circuit which is in a particular clock domain, the reset needs to be synchronized to the clock of the particular domain.

Abstract translation: 公开了一种用于使用同步复位脉冲来复位包括多个时钟域的电路的集成电路和方法。 例如，本公开的方法提供了一个同步到一个时钟的复位信号，采用同步信号并复位多个时钟域中的电路。 为了复位处于特定时钟域的电路的一部分，复位需要与特定域的时钟同步。

公开(公告)号：US09081634B1

公开(公告)日：2015-07-14

申请号：US13672948

申请日：2012-11-09

Applicant: Xilinx, Inc.

Inventor： James M. Simkins ,  Wayne E. Wennekamp ,  John M. Thendean ,  Adam Elkins ,  Richard L. Walke

IPC: G06F7/57

CPC classification number: G06F7/57 ,  G06F7/4806 ,  G06F7/5443 ,  G06F2207/382 ,  G06F2207/3828

Abstract: An apparatus is disclosed. This apparatus includes a digital signal processing (“DSP”) block having a preadder-register block coupled to receive first through fourth input operands. A multiplier is coupled to the preadder-register block to receive a multiplicand operand and a multiplier operand. A first register block is coupled to the multiplier to receive sets of partial products from the multiplier. A second register block coupled to receive the third operand input. An arithmetic logic unit (“ALU”) block is coupled to the pre-adder-register block, the first register block and the second register block. The ALU block includes four input multiplexers and an ALU, where the ALU is coupled to receive outputs from each of the four input multiplexers.

Abstract translation: 公开了一种装置。 该装置包括数字信号处理（“DSP”）块，其具有被耦合以接收第一至第四输入操作数的前置寄存器块。 乘法器耦合到前置寄存器块以接收被乘数的操作数和乘法器操作数。 第一寄存器块耦合到乘法器以从乘法器接收部分乘积的集合。 耦合以接收第三操作数输入的第二寄存器块。 算术逻辑单元（“ALU”）块耦合到预加器寄存器块，第一寄存器块和第二寄存器块。 ALU块包括四个输入多路复用器和一个ALU，其中ALU被耦合以接收四个输入多路复用器中的每一个的输出。

公开(公告)号：US09075930B2

公开(公告)日：2015-07-07

申请号：US13673892

申请日：2012-11-09

Applicant: Xilinx, Inc.

Inventor： Subodh Kumar ,  James M. Simkins ,  Thomas H. Strader ,  Matthew H. Klein ,  James E. Ogden ,  Uma Durairajan

IPC: G11C7/10 ,  G06F13/42 ,  H03K19/177 ,  G11C16/26

CPC classification number: G06F13/4234 ,  G11C7/1006 ,  G11C7/1039 ,  G11C7/1069 ,  G11C7/1096 ,  G11C16/26 ,  G11C2207/104 ,  H03K19/17732 ,  H03K19/1776 ,  Y02D10/14 ,  Y02D10/151

Abstract: An embodiment of a memory module is disclosed. This memory module is a configurable hard macro. A portion of this memory module includes a data input multiplexer coupled to select between cascaded data and direct/bused data. Such portion further includes, a memory coupled to receive output from the data input multiplexer for storage therein, and a register input multiplexer coupled to select between read data from the memory and the cascaded data. This memory module further includes: a register coupled to receive output from the register input multiplexer, a latch/register mode multiplexer coupled to select between the read data from the memory and registered data from the register, and a data output multiplexer coupled to select between the cascaded data and output from the latch/register mode multiplexer to provide output data.

Abstract translation: 公开了一种存储器模块的实施例。 该内存模块是可配置的硬宏。 该存储器模块的一部分包括耦合以在级联数据和直接/传输数据之间进行选择的数据输入多路复用器。 该部分还包括：耦合以从数据输入多路复用器接收输出以存储在其中的存储器，以及耦合以在存储器的读取数据和级联数据之间进行选择的寄存器输入多路复用器。 该存储器模块还包括：耦合以接收来自寄存器输入多路复用器的输出的寄存器，耦合以在来自存储器的读取数据和来自寄存器的寄存数据之间进行选择的锁存/寄存器模式多路复用器，以及数据输出多路复用器， 级联数据和从锁存/寄存器模式多路复用器输出以提供输出数据。

公开(公告)号：US20140133246A1

公开(公告)日：2014-05-15

申请号：US13673892

申请日：2012-11-09

Applicant: Xilinx, Inc.

Inventor： Subodh Kumar ,  James M. Simkins ,  Thomas H. Strader ,  Matthew H. Klein ,  James E. Ogden ,  Uma Durairajan

IPC: G11C7/10 ,  G11C8/00

CPC classification number: G06F13/4234 ,  G11C7/1006 ,  G11C7/1039 ,  G11C7/1069 ,  G11C7/1096 ,  G11C16/26 ,  G11C2207/104 ,  H03K19/17732 ,  H03K19/1776 ,  Y02D10/14 ,  Y02D10/151

Abstract: An embodiment of a memory module is disclosed. This memory module is a configurable hard macro. A portion of this memory module includes a data input multiplexer coupled to select between cascaded data and direct/bused data. Such portion further includes, a memory coupled to receive output from the data input multiplexer for storage therein, and a register input multiplexer coupled to select between read data from the memory and the cascaded data. This memory module further includes: a register coupled to receive output from the register input multiplexer, a latch/register mode multiplexer coupled to select between the read data from the memory and registered data from the register, and a data output multiplexer coupled to select between the cascaded data and output from the latch/register mode multiplexer to provide output data.

Abstract translation: 公开了一种存储器模块的实施例。 该内存模块是可配置的硬宏。 该存储器模块的一部分包括耦合以在级联数据和直接/传输数据之间进行选择的数据输入多路复用器。 该部分还包括：耦合以从数据输入多路复用器接收输出以存储在其中的存储器，以及耦合以在存储器的读取数据和级联数据之间进行选择的寄存器输入多路复用器。 该存储器模块还包括：耦合以接收来自寄存器输入多路复用器的输出的寄存器，耦合以在来自存储器的读取数据和来自寄存器的寄存数据之间进行选择的锁存/寄存器模式多路复用器，以及数据输出多路复用器， 级联数据和从锁存/寄存器模式多路复用器输出以提供输出数据。