公开(公告)号：US20250048648A1

公开(公告)日：2025-02-06

申请号：US18916746

申请日：2024-10-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jia-Rong Wu ,  I-Fan Chang ,  Rai-Min Huang ,  Ya-Huei Tsai ,  Yu-Ping Wang

IPC: H10B61/00 ,  G11C11/16 ,  H01F10/32 ,  H01F41/34 ,  H01L23/522 ,  H01L23/528 ,  H10N50/01 ,  H10N50/80 ,  H10N50/85

Abstract: A semiconductor device includes a substrate having a logic region and a magnetoresistive random access memory (MRAM) region, a magnetic tunneling junction (MTJ) on the MRAM region, a metal interconnection on the MTJ, and a blocking layer on the metal interconnection. Preferably, the blocking layer includes metal and the blocking layer includes a grid line pattern according to a top view.

公开(公告)号：US20230247915A1

公开(公告)日：2023-08-03

申请号：US18132992

申请日：2023-04-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jia-Rong Wu ,  Rai-Min Huang ,  I-Fan Chang ,  Ya-Huei Tsai ,  Yu-Ping Wang

IPC: H10N50/80 ,  H10B61/00 ,  H10N50/01

CPC classification number: H10N50/80 ,  H10B61/22 ,  H10N50/01

Abstract: The present invention provides a semiconductor device, the semiconductor device includes a metal interconnection on a substrate, in which a top view of the metal interconnection comprises a quadrilateral; and a magnetic tunneling junction (MTJ) on the metal interconnection, in which a top view of the MTJ comprises a circular shape, an area of the MTJ is smaller than an area of the metal interconnection.

公开(公告)号：US20220392954A1

公开(公告)日：2022-12-08

申请号：US17888451

申请日：2022-08-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jia-Rong Wu ,  I-Fan Chang ,  Rai-Min Huang ,  Ya-Huei Tsai ,  Yu-Ping Wang

IPC: H01L27/22 ,  G11C11/16 ,  H01F10/32 ,  H01F41/34 ,  H01L23/522 ,  H01L23/528 ,  H01L43/02 ,  H01L43/12

Abstract: A semiconductor device includes a substrate having a logic region and a magnetoresistive random access memory (MRAM) region, a MTJ on the MRAM region, a metal interconnection on the MTJ, and a blocking layer on the metal interconnection. Preferably, the blocking layer includes a stripe pattern according to a top view and the blocking layer could include metal or a dielectric layer.

公开(公告)号：US09679898B2

公开(公告)日：2017-06-13

申请号：US15339945

申请日：2016-11-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Ming Lai ,  Ya-Huei Tsai

IPC: H01L21/00 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/28 ,  H01L21/3213 ,  H01L29/49 ,  H01L29/66 ,  H01L29/51

CPC classification number: H01L27/092 ,  H01L21/28088 ,  H01L21/32134 ,  H01L21/82345 ,  H01L21/8238 ,  H01L21/823842 ,  H01L27/0922 ,  H01L29/49 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

Abstract: A semiconductor device having metal gate includes a first metal gate structure and a second metal gate structure disposed in a first device region and in a second device region on a substrate respectively. The first metal gate structure includes a gate insulating layer, a first bottom barrier layer, a top barrier layer, and a metal layer disposed on the substrate in order, wherein the top barrier layer is directly in contact with the first bottom barrier layer. The second metal gate structure includes the gate insulating layer, a second bottom barrier layer, the top barrier layer, and the metal layer on the substrate in order, wherein the top barrier layer is directly in contact with the second bottom barrier layer. The first bottom barrier layer and the second bottom barrier layer have different impurity compositions.

公开(公告)号：US09524967B1

公开(公告)日：2016-12-20

申请号：US15046458

申请日：2016-02-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hao-Yeh Liu ,  Chien-Ming Lai ,  Yu-Ping Wang ,  Mon-Sen Lin ,  Ya-Huei Tsai ,  Ching-Hsiang Chiu

IPC: H01L27/088 ,  H01L27/092 ,  H01L21/8234

CPC classification number: H01L27/088 ,  H01L21/82345 ,  H01L21/823842 ,  H01L27/092

Abstract: A semiconductor device and a method of forming the same, the semiconductor device include a substrate, and a first transistor, a second transistor and a third transistor all disposed on the substrate. The first transistor includes a first channel, and a first barrier layer and a first work function layer stacked with each other on the first channel. The second transistor includes a second channel, and a second barrier layer and a second work function layer stacked with each other. The third transistor includes a third channel and a third barrier layer and a third work function layer stacked with each other on the third channel, wherein the first barrier layer, the second barrier layer and the third barrier layer have different nitrogen ratio. The first, the second and the third transistors have different threshold voltages, respectively.

Abstract translation: 半导体器件及其形成方法，所述半导体器件包括基板，以及全部设置在所述基板上的第一晶体管，第二晶体管和第三晶体管。 第一晶体管包括第一通道，以及在第一通道上彼此堆叠的第一势垒层和第一功函数层。 第二晶体管包括第二通道，以及彼此堆叠的第二阻挡层和第二功能层。 第三晶体管包括在第三沟道上彼此堆叠的第三沟道和第三势垒层和第三功函数层，其中第一势垒层，第二阻挡层和第三势垒层具有不同的氮比。 第一，第二和第三晶体管分别具有不同的阈值电压。

公开(公告)号：US09412743B2

公开(公告)日：2016-08-09

申请号：US14526552

申请日：2014-10-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Ming Lai ,  Chien-Chung Huang ,  Yu-Ting Tseng ,  Ya-Huei Tsai ,  Yu-Ping Wang

IPC: H01L27/092 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/66 ,  H01L29/51 ,  H01L29/78

CPC classification number: H01L21/823437 ,  H01L21/28088 ,  H01L21/283 ,  H01L21/3211 ,  H01L21/32139 ,  H01L21/823842 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7843

Abstract: The present invention provides a complementary metal oxide semiconductor device, comprising a PMOS and an NMOS. The PMOS has a P type metal gate, which comprises a bottom barrier layer, a P work function metal (PWFM) layer, an N work function tuning (NWFT) layer, an N work function metal (NWFM) layer and a metal layer. The NMOS has an N type metal gate, which comprises the NWFT layer, the NWFM layer and the low-resistance layer. The present invention further provides a method of forming the same.

Abstract translation: 本发明提供一种互补金属氧化物半导体器件，其包括PMOS和NMOS。 PMOS具有P型金属栅极，其包括底部阻挡层，P功函数金属（PWFM）层，N功函数调整（NWFT）层，N功函数金属（NWFM）层和金属层。 NMOS具有N型金属栅极，其包括NWFT层，NWFM层和低电阻层。 本发明还提供一种形成该方法的方法。

公开(公告)号：US09349822B2

公开(公告)日：2016-05-24

申请号：US14543914

申请日：2014-11-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Yang ,  Yu-Feng Liu ,  Jian-Cun Ke ,  Chia-Fu Hsu ,  En-Chiuan Liou ,  Ssu-I Fu ,  Chi-Mao Hsu ,  Nien-Ting Ho ,  Yu-Ru Yang ,  Yu-Ping Wang ,  Chien-Ming Lai ,  Yi-Wen Chen ,  Yu-Ting Tseng ,  Ya-Huei Tsai ,  Chien-Chung Huang ,  Tsung-Yin Hsieh ,  Hung-Yi Wu

IPC: H01L29/49 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/28 ,  H01L21/321 ,  H01L27/092

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/321 ,  H01L21/823431 ,  H01L21/82345 ,  H01L27/088 ,  H01L29/517 ,  H01L29/66545

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having an interlayer dielectric (ILD) layer thereon; forming a first recess, a second recess, and a third recess in the ILD layer; forming a material layer on the ILD layer and in the first recess, the second recess, and the third recess; performing a first treatment on the material layer in the first recess; and performing a second treatment on the material layer in the first recess and second recess.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供其上具有层间电介质（ILD）层的衬底; 在ILD层中形成第一凹槽，第二凹槽和第三凹槽; 在所述ILD层和所述第一凹部，所述第二凹部和所述第三凹部中形成材料层; 对所述第一凹部中的所述材料层进行第一处理; 以及对所述第一凹部和所述第二凹部中的所述材料层进行第二处理。

公开(公告)号：US11665978B2

公开(公告)日：2023-05-30

申请号：US16930291

申请日：2020-07-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jia-Rong Wu ,  Rai-Min Huang ,  I-Fan Chang ,  Ya-Huei Tsai ,  Yu-Ping Wang

IPC: H10N50/80

CPC classification number: H10N50/80 ,  H10B61/22 ,  H10N50/01

Abstract: A method for fabricating a semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a first patterned mask on the first IMD layer, in which the first patterned mask includes a first slot extending along a first direction; forming a second patterned mask on the first patterned mask, in which the second patterned mask includes a second slot extending along a second direction and the first slot intersects the second slot to form a third slot; and forming a first metal interconnection in the third slot.

公开(公告)号：US20210305316A1

公开(公告)日：2021-09-30

申请号：US16857152

申请日：2020-04-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jia-Rong Wu ,  I-Fan Chang ,  Rai-Min Huang ,  Ya-Huei Tsai ,  Yu-Ping Wang

IPC: H01L27/22 ,  H01L43/12 ,  H01L43/02 ,  H01L23/528 ,  H01L23/522 ,  G11C11/16 ,  H01F41/34 ,  H01F10/32

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a logic region and a magnetoresistive random access memory (MRAM) region, forming a magnetic tunneling junction (MTJ) on the MRAM region, forming a metal interconnection on the MTJ, forming a dielectric layer on the metal interconnection, patterning the dielectric layer to form openings, and forming the blocking layer on the patterned dielectric layer and the metal interconnection and into the openings.

公开(公告)号：US20210135092A1

公开(公告)日：2021-05-06

申请号：US16698924

申请日：2019-11-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Po-Kai Hsu ,  Jing-Yin Jhang ,  Hung-Yueh Chen ,  Yu-Ping Wang ,  Jia-Rong Wu ,  Rai-Min Huang ,  Ya-Huei Tsai ,  I-Fan Chang

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/08 ,  H01L43/12

Abstract: A semiconductor device includes a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate and a dummy MTJ between the first MTJ and the second MTJ, in which a bottom surface of the dummy MTJ is not connected to any metal. Preferably, the semiconductor device further includes a first metal interconnection under the first MTJ, a second metal interconnection under the second MTJ, and a first inter-metal dielectric (IMD) layer around the first metal interconnection and the second metal interconnection and directly under the dummy MTJ.