公开(公告)号：US20100236822A1

公开(公告)日：2010-09-23

申请号：US12498860

申请日：2009-07-07

申请人： Toshiki FURUTANI ,  Takeshi FURUSAWA

发明人： Toshiki FURUTANI ,  Takeshi FURUSAWA

IPC分类号： H05K1/18 ,  H05K3/30

CPC分类号： H01L21/4857 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L2224/16 ,  H01L2224/73204 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H05K1/111 ,  H05K1/187 ,  H05K3/205 ,  H05K3/243 ,  H05K3/244 ,  H05K3/428 ,  H05K3/4652 ,  H05K2201/0949 ,  H05K2201/0969 ,  H05K2201/09736 ,  H05K2201/09745 ,  H05K2201/10674 ,  Y10T29/4913 ,  H01L2224/0401

摘要： A wiring board is formed with a substrate, conductive patterns laminated in the thickness direction of the substrate, multiple pads having a predetermined pitch and formed on the same layer as the conductive patterns, a conductive bonding layer arranged on each of the multiple pads, and an electronic component having electrodes. Here, the electronic component is arranged inside the substrate. The electrodes of the electronic component and the multiple pads are electrically connected to each other by means of bonding layers. Also, the height of each of the multiple pads is greater than the height of the conductive pattern adjacent to each pad. Moreover, a protective material related to the bonding layers is not formed at least on the layer where the pads and the first conductive patterns are formed.

摘要翻译： 布线板形成有基板，在基板的厚度方向上层叠的导电图案，具有预定间距的多个焊盘，并形成在与导电图案相同的层上，布置在多个焊盘的每一个上的导电接合层，以及 具有电极的电子部件。 这里，电子部件配置在基板的内部。 电子部件的电极和多个焊盘通过接合层彼此电连接。 此外，多个焊盘中的每一个的高度大于与每个焊盘相邻的导电图案的高度。 此外，至少在形成焊盘和第一导电图案的层上形成与结合层相关的保护材料。

公开(公告)号：US20100108371A1

公开(公告)日：2010-05-06

申请号：US12488177

申请日：2009-06-19

申请人： Toshiki FURUTANI ,  Takeshi FURUSAWA

发明人： Toshiki FURUTANI ,  Takeshi FURUSAWA

IPC分类号： H05K1/16 ,  H05K1/11 ,  H05K3/30

CPC分类号： H05K1/187 ,  H01L21/56 ,  H01L21/563 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/81 ,  H01L2221/68345 ,  H01L2224/0554 ,  H01L2224/05567 ,  H01L2224/05573 ,  H01L2224/056 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81001 ,  H01L2224/81005 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/83005 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15313 ,  H01L2924/3511 ,  H05K3/205 ,  H05K3/3452 ,  H05K3/4602 ,  H05K2201/09909 ,  Y10T29/49133 ,  Y10T29/49144 ,  Y10T29/49146 ,  Y10T29/49204 ,  H01L2224/16225 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A wiring board with a built-in electronic component in which an electronic component is flip-chip mounted to be built in, including a conductive-pattern layer, a connection terminal formed in the conductive-pattern layer and electrically connected to the electronic component, and a solder resist layer formed on the conductive-pattern layer. The solder resist layer is formed around the connection terminal on the conductive-pattern layer, but it is not formed in at least part of the other region on the conductive-pattern layer.

摘要翻译： 一种具有内置电子部件的布线板，其中内置电子部件的内置电子部件，包括导体图案层，形成在导电图案层中并电连接到电子部件的连接端子， 以及形成在导电图案层上的阻焊层。 阻焊层形成在导电图案层上的连接端子周围，但不形成在导电图案层上的其他区域的至少一部分中。

公开(公告)号：US20110001246A1

公开(公告)日：2011-01-06

申请号：US12883031

申请日：2010-09-15

申请人： Takeshi FURUSAWA ,  Takao Kamoshima ,  Masatsugu Amishiro ,  Naohito Suzumura ,  Shoichi Fukui ,  Masakazu Okada

发明人： Takeshi FURUSAWA ,  Takao Kamoshima ,  Masatsugu Amishiro ,  Naohito Suzumura ,  Shoichi Fukui ,  Masakazu Okada

IPC分类号： H01L23/48

CPC分类号： H01L21/76832 ,  H01L21/76834 ,  H01L21/76883

摘要： The reliability of a semiconductor device having an embedded wire in the lowest layer wire is improved. In a main surface of a semiconductor substrate, MISFETs are formed and over the main surface, insulating films 10, 11 are formed. In the insulating films 10, 11 a contact hole is formed and a plug is embedded therein. Over the insulating film 11 in which the plug is embedded, insulating films 14, 15, 16 are formed and an opening is formed in the insulating films 14, 15, 16 and a wire is embedded therein. The insulating film 15 is an etching stopper film when etching the insulating film 16 in order to form the opening, containing silicon and carbon. The insulating film 11 has a high hygroscopicity and the insulating film 15 has a low moisture resistance, however, by interposing the insulating film 14 therebetween and making the insulating film 14 have a higher density of the number of Si (silicon) atoms than that of the insulating film 11, an electrically weak interface is prevented from being formed.

摘要翻译： 提高了在最低层布线中具有嵌入线的半导体器件的可靠性。 在半导体衬底的主表面中，形成MISFET，并且在主表面上形成绝缘膜10,11。 在绝缘膜10,11中形成有接触孔，并且插入插头。 在插入插头的绝缘膜11上形成绝缘膜14,15,16，并且在绝缘膜14,15,16中形成开口，并且在其中嵌入线。 绝缘膜15是在蚀刻绝缘膜16以形成包含硅和碳的开口时的蚀刻停止膜。 绝缘膜11具有高的吸湿性，绝缘膜15具有低的耐湿性，然而，通过在其间插入绝缘膜14，使得绝缘膜14具有比Si（硅）原子数更高的Si（硅）原子数 绝缘膜11，电阻弱的界面被防止形成。

公开(公告)号：US20070167010A1

公开(公告)日：2007-07-19

申请号：US11622767

申请日：2007-01-12

申请人： Takeshi FURUSAWA ,  Daisuke KODAMA ,  Masahiro MATSUMOTO ,  Hiroshi MIYAZAKI

发明人： Takeshi FURUSAWA ,  Daisuke KODAMA ,  Masahiro MATSUMOTO ,  Hiroshi MIYAZAKI

IPC分类号： H01L21/44

CPC分类号： H01L21/76843 ,  H01L21/76805 ,  H01L21/76844 ,  H01L21/76877 ,  H01L21/76886 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： To provide a semiconductor device having a structure in which a barrier metal film containing nitrogen is formed in a connection surface between a copper alloy wiring and a via, in which the electric resistance between the copper alloy wiring and the via can be prevented from rising, and the electric resistance can be prevented from varying. A semiconductor device according to the present invention comprises a first copper alloy wiring, a via and a first barrier metal film. The first copper alloy wiring is formed in an interlayer insulation film and contains a predetermined additive element in a main component Cu. The via is formed in an interlayer insulation film and electrically connected to the upper surface of the first copper alloy wiring. The first barrier metal film is formed so as to be in contact with the first copper alloy wiring in the connection part between the first copper alloy wiring and the via and contains nitrogen. The predetermined additive element reacts with nitrogen to form a high-resistance part. In addition, the concentration of the predetermined additive element is not more than 0.04 wt %.

摘要翻译： 为了提供一种半导体器件，其具有在铜合金布线和通孔之间的连接面上形成含有氮的阻挡金属膜的结构，其中可以防止铜合金布线和通孔之间的电阻上升， 并且可以防止电阻变化。 根据本发明的半导体器件包括第一铜合金布线，通孔和第一阻挡金属膜。 第一铜合金布线形成在层间绝缘膜中，并且在主要成分Cu中含有预定的添加元素。 通孔形成在层间绝缘膜中并与第一铜合金布线的上表面电连接。 第一阻挡金属膜形成为与第一铜合金布线和通孔之间的连接部分中的第一铜合金布线接触并且包含氮。 预定的添加元素与氮反应形成高电阻部分。 此外，预定添加元素的浓度不大于0.04重量％。

公开(公告)号：US20090263963A1

公开(公告)日：2009-10-22

申请号：US12493347

申请日：2009-06-29

申请人： Takeshi FURUSAWA ,  Noriko Miura ,  Kinya Goto ,  Masazumi Matsuura

发明人： Takeshi FURUSAWA ,  Noriko Miura ,  Kinya Goto ,  Masazumi Matsuura

IPC分类号： H01L21/768

CPC分类号： H01L21/76802 ,  H01L21/02074 ,  H01L21/02126 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/0234 ,  H01L21/02362 ,  H01L21/3105 ,  H01L21/31633 ,  H01L21/76801 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76835 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： In a semiconductor having a multilayer wiring structure device on a semiconductor substrate, the multilayer wiring structure includes an interlayer insulating film having at least an organic siloxane insulating film. The organic siloxane insulating film has a relative dielectric constant of 3.1 or less, a hardness of 2.7 GPa or more, and a ratio of carbon atoms to silicon atoms between 0.5 and 1.0, inclusive. Further, the multilayer wiring structure may include an insulating layer having a ratio of carbon atoms to silicon atoms not greater than 0.1, the insulating layer being formed on the top surface of the organic siloxane insulating film as a result of carbon leaving the organic siloxane insulating film.

摘要翻译： 在半导体衬底上具有多层布线结构器件的半导体中，多层布线结构包括至少具有有机硅氧烷绝缘膜的层间绝缘膜。 有机硅氧烷绝缘膜的相对介电常数为3.1以下，硬度为2.7GPa以上，碳原子与硅原子的比例在0.5以上且1.0以下。 此外，多层布线结构可以包括碳原子与硅原子之比不大于0.1的绝缘层，绝缘层由有机硅氧烷绝缘膜的碳离子形成在有机硅氧烷绝缘膜的顶表面上 电影。

公开(公告)号：US20090189245A1

公开(公告)日：2009-07-30

申请号：US12410170

申请日：2009-03-24

申请人： Takeshi FURUSAWA ,  Noriko Miura ,  Kinya Goto ,  Masazumi Matsuura

发明人： Takeshi FURUSAWA ,  Noriko Miura ,  Kinya Goto ,  Masazumi Matsuura

IPC分类号： H01L23/58

CPC分类号： H01L23/585 ,  H01L23/3192 ,  H01L23/53295 ,  H01L23/564 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device according to the invention is a semiconductor device which includes a low dielectric constant film of which the relative dielectric constant is less than 3.5, is provided with one or more seal rings that are moisture blocking walls in closed loop form in a plan view, and where at least one of the seal rings includes a seal ring protrusion portion in inward protruding form in the vicinity of a chip corner.

摘要翻译： 根据本发明的半导体器件是一种半导体器件，其包括相对介电常数小于3.5的低介电常数膜，在平面图中设置有一个或多个密闭环，其为闭环形式的防潮壁 并且其中至少一个所述密封环包括在芯片角附近以向内突出形式的密封环突出部分。

公开(公告)号：US20120289032A1

公开(公告)日：2012-11-15

申请号：US13476471

申请日：2012-05-21

申请人： Takeshi FURUSAWA ,  Takao KAMOSHIMA ,  Masatsugu AMISHIRO ,  Naohito SUZUMURA ,  Shoichi FUKUI ,  Masakazu OKADA

发明人： Takeshi FURUSAWA ,  Takao KAMOSHIMA ,  Masatsugu AMISHIRO ,  Naohito SUZUMURA ,  Shoichi FUKUI ,  Masakazu OKADA

IPC分类号： H01L21/20

CPC分类号： H01L21/76832 ,  H01L21/76834 ,  H01L21/76883

摘要： The reliability of a semiconductor device having an embedded wire in the lowest layer wire is improved. In a main surface of a semiconductor substrate, MISFETs are formed. Over the main surface, insulating films 10, 11 are formed. In the insulating films 10, 11 a contact hole is formed and a plug is embedded therein. Over the insulating film 11, insulating films 14, 15, 16 are formed. An opening is formed in those insulating films and a wire is embedded therein. The insulating film 15 is an etching stopper film when etching the insulating film 16 to form the opening. The insulating film 11 has a high hygroscopicity and the insulating film 15 has a low moisture resistance. By interposing the insulating film 14 therebetween with a higher density of Si (silicon) atoms than the insulating film 11, an electrically weak interface is prevented from being formed.

摘要翻译： 提高了在最低层布线中具有嵌入线的半导体器件的可靠性。 在半导体衬底的主表面中形成MISFET。 在主表面上形成绝缘膜10,11。 在绝缘膜10,11中形成有接触孔，并且插入插头。 在绝缘膜11上形成绝缘膜14,15,16。 在这些绝缘膜中形成开口，并且在其中嵌入线。 当蚀刻绝缘膜16以形成开口时，绝缘膜15是蚀刻停止膜。 绝缘膜11具有高吸湿性，绝缘膜15具有低的耐湿性。 通过在绝缘膜14之间插入比绝缘膜11高的Si（硅）原子密度，可以防止形成电性弱的界面。

公开(公告)号：US20100327449A1

公开(公告)日：2010-12-30

申请号：US12880520

申请日：2010-09-13

申请人： Takeshi FURUSAWA ,  Daisuke Kodama ,  Masahiro Matsumoto ,  Hiroshi Miyazaki

发明人： Takeshi FURUSAWA ,  Daisuke Kodama ,  Masahiro Matsumoto ,  Hiroshi Miyazaki

IPC分类号： H01L23/532 ,  H01L21/768

CPC分类号： H01L21/76843 ,  H01L21/76805 ,  H01L21/76844 ,  H01L21/76877 ,  H01L21/76886 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： To provide a semiconductor device having a structure in which a barrier metal film containing nitrogen is formed in a connection surface between a copper alloy wiring and a via, in which the electric resistance between the copper alloy wiring and the via can be prevented from rising, and the electric resistance can be prevented from varying. A semiconductor device according to the present invention comprises a first copper alloy wiring, a via and a first barrier metal film. The first copper alloy wiring is formed in an interlayer insulation film and contains a predetermined additive element in a main component Cu. The via is formed in an interlayer insulation film and electrically connected to the upper surface of the first copper alloy wiring. The first barrier metal film is formed so as to be in contact with the first copper alloy wiring in the connection part between the first copper alloy wiring and the via and contains nitrogen. The predetermined additive element reacts with nitrogen to form a high-resistance part. In addition, the concentration of the predetermined additive element is not more than 0.04 wt %.

摘要翻译： 为了提供一种半导体器件，其具有在铜合金布线和通孔之间的连接面上形成含有氮的阻挡金属膜的结构，其中可以防止铜合金布线和通孔之间的电阻上升， 并且可以防止电阻变化。 根据本发明的半导体器件包括第一铜合金布线，通孔和第一阻挡金属膜。 第一铜合金布线形成在层间绝缘膜中，并且在主要成分Cu中含有预定的添加元素。 通孔形成在层间绝缘膜中并与第一铜合金布线的上表面电连接。 第一阻挡金属膜形成为与第一铜合金布线和通孔之间的连接部分中的第一铜合金布线接触并且包含氮。 预定的添加元素与氮反应形成高电阻部分。 此外，预定添加元素的浓度不大于0.04重量％。

公开(公告)号：US20100314620A1

公开(公告)日：2010-12-16

申请号：US12794739

申请日：2010-06-05

申请人： Takeshi FURUSAWA ,  Takao Kamoshima ,  Hiroki Takewaka

发明人： Takeshi FURUSAWA ,  Takao Kamoshima ,  Hiroki Takewaka

IPC分类号： H01L23/48

CPC分类号： H01L22/32 ,  H01L21/768 ,  H01L23/53223 ,  H01L23/53238 ,  H01L24/05 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05073 ,  H01L2224/05093 ,  H01L2224/05166 ,  H01L2224/05187 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/45147 ,  H01L2224/48847 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/1306 ,  H01L2924/3011 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2224/48824 ,  H01L2924/00

摘要： To suppress or prevent the generation of a crack in an insulating film below an external terminal which could be caused by an external force added to the external terminal of a semiconductor device. A top wiring layer MH of wiring layers formed on a main surface of a silicon substrate has a pad comprising a conductor pattern containing aluminum. On an undersurface of the pad, there are arranged a barrier conductor film formed by laminating, from below, a first barrier conductor film and a second barrier conductor film. Of a fifth wiring layer which is one layer lower than the top wiring layer, in an area overlapping with a probe contact area of the pad in a plane, the conductor pattern is not arranged. Further, the first and second barrier conductor films are the conductor films including titanium and titanium nitride as principal components, respectively. Also, the first barrier conductor film is thicker than the second barrier conductor film.

摘要翻译： 抑制或防止在外部端子下面的绝缘膜中产生裂纹，该绝缘膜可能由于加到半导体器件的外部端子上的外力引起。 形成在硅衬底的主表面上的布线层的顶部布线层MH具有包括含有铝的导体图案的衬垫。 在焊盘的下表面上，设置有由第一阻挡导体膜和第二阻挡导体膜从下方层叠形成的阻挡导体膜。 在比顶部布线层低一层的第五布线层中，在与平面中的焊盘的探针接触区域重叠的区域中，不布置导体图案。 此外，第一和第二阻挡导体膜分别是包括钛和氮化钛作为主要成分的导体膜。 此外，第一阻挡导体膜比第二阻挡导体膜厚。