公开(公告)号：US08963291B2

公开(公告)日：2015-02-24

申请号：US13112738

申请日：2011-05-20

Applicant: Takeshi Furusawa ,  Noriko Miura ,  Kinya Goto ,  Masazumi Matsuura

Inventor： Takeshi Furusawa ,  Noriko Miura ,  Kinya Goto ,  Masazumi Matsuura

IPC: H01L21/56

CPC classification number: H01L23/585 ,  H01L23/3192 ,  H01L23/53295 ,  H01L23/564 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device including a low dielectric constant film of which the relative dielectric constant is less than 3.5, is provided with one or more seal rings that are moisture blocking walls forming a closed loop in a plan view, and where at least one of the seal rings includes a seal ring protrusion portion in inward protruding form in the vicinity of a chip corner.

Abstract translation: 包括相对介电常数小于3.5的低介电常数膜的半导体器件设置有一个或多个密封环，该密封环是在平面图中形成闭环的防潮壁，并且其中至少一个密封件 环在芯片角附近包括向内突出形式的密封环突出部。

公开(公告)号：US08018030B2

公开(公告)日：2011-09-13

申请号：US12410170

申请日：2009-03-24

Applicant: Takeshi Furusawa ,  Noriko Miura ,  Kinya Goto ,  Masazumi Matsuura

Inventor： Takeshi Furusawa ,  Noriko Miura ,  Kinya Goto ,  Masazumi Matsuura

IPC: H01L21/56

CPC classification number: H01L23/585 ,  H01L23/3192 ,  H01L23/53295 ,  H01L23/564 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device according to the invention is a semiconductor device which includes a low dielectric constant film of which the relative dielectric constant is less than 3.5, is provided with one or more seal rings that are moisture blocking walls in closed loop form in a plan view, and where at least one of the seal rings includes a seal ring protrusion portion in inward protruding form in the vicinity of a chip corner.

Abstract translation: 根据本发明的半导体器件是一种半导体器件，其包括相对介电常数小于3.5的低介电常数膜，在平面图中设置有一个或多个密闭环，其为闭环形式的防潮壁 并且其中至少一个所述密封环包括在芯片角附近以向内突出形式的密封环突出部分。

公开(公告)号：US07960279B2

公开(公告)日：2011-06-14

申请号：US12493347

申请日：2009-06-29

Applicant: Takeshi Furusawa ,  Noriko Miura ,  Kinya Goto ,  Masazumi Matsuura

Inventor： Takeshi Furusawa ,  Noriko Miura ,  Kinya Goto ,  Masazumi Matsuura

IPC: H01L21/44

CPC classification number: H01L21/76802 ,  H01L21/02074 ,  H01L21/02126 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/0234 ,  H01L21/02362 ,  H01L21/3105 ,  H01L21/31633 ,  H01L21/76801 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76835 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

Abstract: In a semiconductor having a multilayer wiring structure device on a semiconductor substrate, the multilayer wiring structure includes an interlayer insulating film having at least an organic siloxane insulating film. The organic siloxane insulating film has a relative dielectric constant of 3.1 or less, a hardness of 2.7 GPa or more, and a ratio of carbon atoms to silicon atoms between 0.5 and 1.0, inclusive. Further, the multilayer wiring structure may include an insulating layer having a ratio of carbon atoms to silicon atoms not greater than 0.1, the insulating layer being formed on the top surface of the organic siloxane insulating film as a result of carbon leaving the organic siloxane insulating film.

Abstract translation: 在半导体衬底上具有多层布线结构器件的半导体中，多层布线结构包括至少具有有机硅氧烷绝缘膜的层间绝缘膜。 有机硅氧烷绝缘膜的相对介电常数为3.1以下，硬度为2.7GPa以上，碳原子与硅原子的比例在0.5以上且1.0以下。 此外，多层布线结构可以包括碳原子与硅原子之比不大于0.1的绝缘层，绝缘层由有机硅氧烷绝缘膜的碳离子形成在有机硅氧烷绝缘膜的顶表面上 电影。

公开(公告)号：US20100112805A1

公开(公告)日：2010-05-06

申请号：US12683949

申请日：2010-01-07

Applicant: Teruhiko Kumada ,  Hideharu Nobutoki ,  Naoki Yasuda ,  Kinya Goto ,  Masazumi Matsuura

Inventor： Teruhiko Kumada ,  Hideharu Nobutoki ,  Naoki Yasuda ,  Kinya Goto ,  Masazumi Matsuura

IPC: H01L21/768

CPC classification number: H01L21/02271 ,  H01L21/314 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76835

Abstract: There is provided a semiconductor device and method of fabricating the same that employs an insulation film of a borazine-based compound to provided enhanced contact between a material for insulation and that for interconnection, increased mechanical strength, and other improved characteristics. The semiconductor device includes a first insulation layer having a recess with a first conductor layer buried therein, an etching stopper layer formed on the first insulation layer, a second insulation layer formed on the etching stopper layer, a third insulation layer formed on the second insulation layer, and a second conductor layer buried in a recess of the second and third insulation layers. The second and third insulation layers are grown by chemical vapor deposition with a carbon-containing borazine compound used as a source material and the third insulation layer is smaller in carbon content than the second insulation layer.

Abstract translation: 提供一种半导体器件及其制造方法，其采用环硼氮烷化合物的绝缘膜，以提供绝缘材料和互连材料，增加的机械强度和其它改进的特性之间的增强的接触。 半导体器件包括具有埋设有第一导体层的凹部的第一绝缘层，形成在第一绝缘层上的蚀刻阻挡层，形成在蚀刻停止层上的第二绝缘层，形成在第二绝缘层上的第三绝缘层 层，以及埋在第二绝缘层和第三绝缘层的凹部中的第二导体层。 第二绝缘层和第三绝缘层通过化学气相沉积生长，其中含有碳源的环硼氮烷化合物用作源材料，第三绝缘层的碳含量比第二绝缘层小。

公开(公告)号：US20080093709A1

公开(公告)日：2008-04-24

申请号：US11907998

申请日：2007-10-19

Applicant: Masazumi Matsuura ,  Kinya Goto ,  Hisashi Yano ,  Kotaro Nomura

Inventor： Masazumi Matsuura ,  Kinya Goto ,  Hisashi Yano ,  Kotaro Nomura

IPC: H01L21/42 ,  H01L23/58

CPC classification number: H01L21/428 ,  H01L29/78

Abstract: A semiconductor substrate in a state that an inter-layer insulation film is formed is loaded in a chamber, air in the chamber is purged by introducing a large amount of a nitrogen gas in the chamber, and an atmospheric gas in the chamber is substituted with a nitrogen gas. After that, UV cure is performed by introducing a small amount of an oxygen gas adjusted to an atmospheric pressure or a little more positive pressure in the chamber by nitrogen purge. For the introduction of an oxygen gas, an oxygen gas is introduced while controlling the flow rate by using a flow meter, and adjustment is performed using the flow meter so that the oxygen concentration in the chamber becomes a constant value in the range of 5 ppm to 400 ppm.

Abstract translation: 将形成有层间绝缘膜的状态的半导体基板载置在室内，通过在室内引入大量的氮气来吹扫室内的空气，将室内的气氛气体置换为 氮气。 之后，通过氮气吹扫在腔室内引入少量调节至大气压或稍微正压的氧气来进行UV固化。 为了引入氧气，引入氧气，同时通过使用流量计来控制流量，并且使用流量计进行调节，使得室中的氧浓度变为在5ppm范围内的恒定值 至400ppm。

公开(公告)号：US20070114668A1

公开(公告)日：2007-05-24

申请号：US11561629

申请日：2006-11-20

Applicant: Kinya Goto ,  Takeshi Furusawa ,  Masazumi Matsuura ,  Noriko Miura

Inventor： Kinya Goto ,  Takeshi Furusawa ,  Masazumi Matsuura ,  Noriko Miura

IPC: H01L23/52

CPC classification number: H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05093 ,  H01L2224/05096 ,  H01L2224/05147 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05553 ,  H01L2224/05624 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48463 ,  H01L2224/48799 ,  H01L2224/49175 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/04953 ,  H01L2924/30105 ,  H01L2924/00014 ,  H01L2924/04941 ,  H01L2924/00 ,  H01L2224/48824 ,  H01L2924/00015

Abstract: A semiconductor device is equipped with a semiconductor chip which has at least one layer of first insulating film formed on a substrate, and a plurality of pads arranged on a layer higher than the first insulating film. The plurality of pads on the semiconductor chip are arranged parallel to a predetermined chip edge of the semiconductor chip. The first insulating film has a reinforcement pattern in a region underneath each of the plurality of pads. In the region underneath each pad, occupancy of the reinforcement pattern in the first insulating film is within a predetermined range permitted for the region underneath each pad and occupancy of the reinforcement pattern in a whole area of a row where the reinforcement pattern is arranged in a line in a direction perpendicular to the predetermined chip edge is higher than occupancy of the reinforcement pattern in a whole area of a row where the reinforcement pattern is arranged in a line in a direction parallel to the chip edge.

Abstract translation: 半导体器件配备有半导体芯片，该半导体芯片具有形成在基板上的至少一层第一绝缘膜，以及布置在高于第一绝缘膜的层上的多个焊盘。 半导体芯片上的多个焊盘平行于半导体芯片的预定的芯片边缘布置。 第一绝缘膜在多个焊盘中的每一个下方的区域中具有加强图案。 在每个垫下面的区域中，第一绝缘膜中的加强图案的占用在每个垫下面的区域允许的预定范围内，并且在加强图案布置在一排中的整个区域中的加强图案的占用 在垂直于预定芯片边缘的方向上的线在高于在与芯片边缘平行的方向上排列成一列的行的整个区域中的加强图案的占有率高。

公开(公告)号：US06399424B1

公开(公告)日：2002-06-04

申请号：US09663201

申请日：2000-09-18

Applicant: Masazumi Matsuura ,  Kinya Goto ,  Noboru Morimoto

Inventor： Masazumi Matsuura ,  Kinya Goto ,  Noboru Morimoto

IPC: H01L2144

CPC classification number: H01L21/76811 ,  H01L21/76801 ,  H01L21/76813 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Implemented is a method of manufacturing a contact structure having a combination of formation of a buried wiring and that of a low dielectric constant interlayer insulating film in which a connecting hole to be formed in a low dielectric constant interlayer insulating film does not turn into an abnormal shape. A fourth interlayer insulating film 11 is formed on an upper surface of a third interlayer insulating film 10. Next, patterning for a wiring trench and a connecting hole is carried out into the fourth interlayer insulating film 11 and the third interlayer insulating film 10, respectively. Then, a pattern of the connecting hole is first formed in a third low dielectric constant interlayer insulating film 9. Thereafter, a second interlayer insulating film 8 exposed in the pattern is removed and a pattern of the wiring trench is formed in the third interlayer insulating film 10. Subsequently, second and third low dielectric constant interlayer insulating films 7 and 9 are etched, and the wiring trench and the connecting hole are formed at the same time. Thus, a photoresist can be formed again without the second and third low dielectric constant interlayer insulating films 7 and 9 exposed, and an abnormal shape is generated in the connecting hole with difficulty.

Abstract translation: 具体实施方式是制造具有掩埋布线的形成和低介电常数层间绝缘膜的组合的接触结构的方法，其中形成在低介电常数层间绝缘膜中的连接孔不会变成异常 形状。 第四层间绝缘膜11形成在第三层间绝缘膜10的上表面上。接下来，分别对第四层间绝缘膜11和第三层间绝缘膜10进行布线沟槽和连接孔的图案化 。 然后，首先在第三低介电常数层间绝缘膜9中形成连接孔的图案。然后，去除以图案露出的第二层间绝缘膜8，并且在第三层间绝缘层中形成布线沟槽的图案 随后，蚀刻第二和第三低介电常数层间绝缘膜7和9，并且同时形成布线沟槽和连接孔。 因此，可以再次形成光致抗蚀剂，而不会使第二和第三低介电常数层间绝缘膜7和9暴露，并且难以在连接孔中产生异常形状。

公开(公告)号：US20110215447A1

公开(公告)日：2011-09-08

申请号：US13112738

申请日：2011-05-20

Applicant: Takeshi Furusawa ,  Norio Miura ,  Kinya Goto ,  Masazumi Matsuura

Inventor： Takeshi Furusawa ,  Norio Miura ,  Kinya Goto ,  Masazumi Matsuura

IPC: H01L23/58

CPC classification number: H01L23/585 ,  H01L23/3192 ,  H01L23/53295 ,  H01L23/564 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device including a low dielectric constant film of which the relative dielectric constant is less than 3.5, is provided with one or more seal rings that are moisture blocking walls forming a closed loop in a plan view, and where at least one of the seal rings includes a seal ring protrusion portion in inward protruding form in the vicinity of a chip corner.

Abstract translation: 包括相对介电常数小于3.5的低介电常数膜的半导体器件设置有一个或多个密封环，该密封环是在平面图中形成闭环的防潮壁，并且其中至少一个密封件 环在芯片角附近包括向内突出形式的密封环突出部。

公开(公告)号：US07671473B2

公开(公告)日：2010-03-02

申请号：US11452376

申请日：2006-06-14

Applicant: Teruhiko Kumada ,  Hideharu Nobutoki ,  Naoki Yasuda ,  Kinya Goto ,  Masazumi Matsuura

Inventor： Teruhiko Kumada ,  Hideharu Nobutoki ,  Naoki Yasuda ,  Kinya Goto ,  Masazumi Matsuura

IPC: H01L23/48

CPC classification number: H01L21/02271 ,  H01L21/314 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76835

Abstract: There is provided a semiconductor device and method of fabricating the same that employs an insulation film of a borazine-based compound to provided enhanced contact between a material for insulation and that for interconnection, increased mechanical strength, and other improved characteristics. The semiconductor device includes a first insulation layer having a recess with a first conductor layer buried therein, an etching stopper layer formed on the first insulation layer, a second insulation layer formed on the etching stopper layer, a third insulation layer formed on the second insulation layer, and a second conductor layer buried in a recess of the second and third insulation layers. The second and third insulation layers are grown by chemical vapor deposition with a carbon-containing borazine compound used as a source material and the third insulation layer is smaller in carbon content than the second insulation layer.

Abstract translation: 提供一种半导体器件及其制造方法，其采用环硼氮烷化合物的绝缘膜，以提供绝缘材料和互连材料，增加的机械强度和其它改进的特性之间的增强的接触。 半导体器件包括具有埋设有第一导体层的凹部的第一绝缘层，形成在第一绝缘层上的蚀刻阻挡层，形成在蚀刻停止层上的第二绝缘层，形成在第二绝缘层上的第三绝缘层 层，以及埋在第二绝缘层和第三绝缘层的凹部中的第二导体层。 第二绝缘层和第三绝缘层通过化学气相沉积生长，其中含有碳源的环硼氮烷化合物用作源材料，第三绝缘层的碳含量比第二绝缘层小。

公开(公告)号：US20060286814A1

公开(公告)日：2006-12-21

申请号：US11452376

申请日：2006-06-14

Applicant: Teruhiko Kumada ,  Hideharu Nobutoki ,  Naoki Yasuda ,  Kinya Goto ,  Masazumi Matsuura

Inventor： Teruhiko Kumada ,  Hideharu Nobutoki ,  Naoki Yasuda ,  Kinya Goto ,  Masazumi Matsuura

IPC: H01L31/00 ,  H01L21/336

CPC classification number: H01L21/02271 ,  H01L21/314 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76835

Abstract: There is provided a semiconductor device and method of fabricating the same that employs an insulation film of a borazine-based compound to provided enhanced contact between a material for insulation and that for interconnection, increased mechanical strength, and other improved characteristics. The semiconductor device includes a first insulation layer having a recess with a first conductor layer buried therein, an etching stopper layer formed on the first insulation layer, a second insulation layer formed on the etching stopper layer, a third insulation layer formed on the second insulation layer, and a second conductor layer buried in a recess of the second and third insulation layers. The second and third insulation layers are grown by chemical vapor deposition with a carbon-containing borazine compound used as a source material and the third insulation layer is smaller in carbon content than the second insulation layer.

Abstract translation: 提供一种半导体器件及其制造方法，其采用环硼氮烷化合物的绝缘膜，以提供绝缘材料和互连材料，增加的机械强度和其它改进的特性之间的增强的接触。 半导体器件包括具有埋设有第一导体层的凹部的第一绝缘层，形成在第一绝缘层上的蚀刻阻挡层，形成在蚀刻停止层上的第二绝缘层，形成在第二绝缘层上的第三绝缘层 层，以及埋在第二绝缘层和第三绝缘层的凹部中的第二导体层。 第二绝缘层和第三绝缘层通过化学气相沉积生长，其中含有碳源的环硼氮烷化合物用作源材料，第三绝缘层的碳含量比第二绝缘层小。