Invention Grant
- Patent Title: Semiconductor chip with seal ring and sacrificial corner pattern
- Patent Title (中): 半导体芯片具有密封圈和牺牲角图案
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Application No.: US13112738Application Date: 2011-05-20
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Publication No.: US08963291B2Publication Date: 2015-02-24
- Inventor: Takeshi Furusawa , Noriko Miura , Kinya Goto , Masazumi Matsuura
- Applicant: Takeshi Furusawa , Noriko Miura , Kinya Goto , Masazumi Matsuura
- Applicant Address: JP Kawasaki-shi
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kawasaki-shi
- Agency: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2004-264014 20040910
- Main IPC: H01L21/56
- IPC: H01L21/56
Abstract:
A semiconductor device including a low dielectric constant film of which the relative dielectric constant is less than 3.5, is provided with one or more seal rings that are moisture blocking walls forming a closed loop in a plan view, and where at least one of the seal rings includes a seal ring protrusion portion in inward protruding form in the vicinity of a chip corner.
Public/Granted literature
- US20110215447A1 SEMICONDUCTOR CHIP WITH SEAL RING AND SACRIFICIAL CORNER PATTERN Public/Granted day:2011-09-08
Information query
IPC分类:
