公开(公告)号：US09032235B2

公开(公告)日：2015-05-12

申请号：US13727984

申请日：2012-12-27

Applicant: Toshikatsu Hida ,  Mitsunori Tadokoro

Inventor： Toshikatsu Hida ,  Mitsunori Tadokoro

IPC: G06F1/00 ,  G06F1/32 ,  G06F12/00 ,  G06F11/00

CPC classification number: G06F1/3275 ,  G06F1/3225 ,  G06F1/3287 ,  Y02D10/13 ,  Y02D10/14

Abstract: According to one embodiment, a semiconductor storage device includes a nonvolatile memory, memory controller storing control information, a switch between the nonvolatile memory/memory controller and a power supply terminal, a second memory, an interpreter interprets a command, a switch controller, and a third memory stores an address of the control information in the second memory. The memory controller instructs the switch controller to open the switch after writing the control information into the second memory and reads the control information from the second memory based on the address stored in the third memory when the memory controller is electrically connected to the first power supply terminal.

Abstract translation: 根据一个实施例，半导体存储装置包括非易失性存储器，存储控制信息的存储器控​​制器，非易失性存储器/存储器控制器和电源端子之间的切换，第二存储器，解释器解释命令，开关控制器和 第三存储器将控制信息的地址存储在第二存储器中。 当存储器控制器电连接到第一电源时，存储器控制器指示开关控制器在将控制信息写入第二存储器之后打开开关，并且基于存储在第三存储器中的地址从第二存储器读取控制信息 终奌站。

公开(公告)号：US09331713B2

公开(公告)日：2016-05-03

申请号：US13600929

申请日：2012-08-31

Applicant: Yoshiki Saito ,  Shinichi Kanno ,  Toshikatsu Hida

Inventor： Yoshiki Saito ,  Shinichi Kanno ,  Toshikatsu Hida

IPC: H03M13/05 ,  H03M13/00

CPC classification number: H03M13/05 ,  H03M13/6516

Abstract: According to an embodiment, an encoding apparatus includes a parameter holding unit configured to hold a parameter; an error-detecting code holding unit configured to hold an error-detecting code that is generated from the parameter; an error detecting unit configured to detect an error in the parameter, which is held in the parameter holding unit, with the use of the error-detecting code held in the error-detecting code holding unit; an error correcting unit configured to correct the error detected by the error detecting unit; a selecting unit configured to select the parameter that has been subjected to error correction by the error correcting unit; and an encoding unit configured to encode data with the use of the parameter selected by the selecting unit.

Abstract translation: 根据实施例，一种编码装置包括：配置为保存参数的参数保持单元; 错误检测码保持单元，被配置为保存从该参数生成的检错码; 错误检测单元，被配置为使用保持在错误检测码保持单元中的检错码来检测保存在参数保持单元中的参数中的错误; 错误校正单元，被配置为校正由所述错误检测单元检测到的所述错误; 选择单元，被配置为通过误差校正单元选择已经经过纠错的参数; 以及编码单元，被配置为使用由所述选择单元选择的参数来对数据进行编码。

公开(公告)号：US08868842B2

公开(公告)日：2014-10-21

申请号：US13063210

申请日：2009-12-28

Applicant: Hirokuni Yano ,  Ryoichi Kato ,  Toshikatsu Hida

Inventor： Hirokuni Yano ,  Ryoichi Kato ,  Toshikatsu Hida

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F12/12 ,  G06F12/08 ,  G11C16/10 ,  G11C16/04 ,  G06F12/02

CPC classification number: G06F12/0804 ,  G06F12/0246 ,  G06F12/0866 ,  G06F12/126 ,  G06F12/128 ,  G06F2212/2022 ,  G06F2212/7201 ,  G11C16/0483 ,  G11C16/10

Abstract: A WC resource usage is compared with an auto flush (AU) threshold Caf that is smaller than an upper limit Clmt, and when the WC resource usage exceeds the AF threshold Caf, the organizing state of a NAND memory 10 is checked. When the organizing of the NAND memory 10 has proceeded sufficiently, data is flushed from a write cache (WC) 21 to the NAND memory 10 early, so that the response to the subsequent write command is improved.

Abstract translation: 将WC资源使用与小于上限Clmt的自动刷新（AU）阈值Caf进行比较，并且当WC资源使用超过AF阈值Caf时，检查NAND存储器10的组织状态。 当NAND存储器10的组织已经充分进行时，数据从写高速缓冲存储器（WC）21快速刷新到NAND存储器10，从而提高对后续写命令的响应。

公开(公告)号：US08583972B2

公开(公告)日：2013-11-12

申请号：US13486718

申请日：2012-06-01

Applicant: Toshikatsu Hida ,  Shinichi Kanno ,  Hirokuni Yano ,  Kazuya Kitsunai ,  Shigehiro Asano ,  Junji Yano

Inventor： Toshikatsu Hida ,  Shinichi Kanno ,  Hirokuni Yano ,  Kazuya Kitsunai ,  Shigehiro Asano ,  Junji Yano

IPC: G11C29/00

CPC classification number: G06F11/1412 ,  G06F11/1068 ,  G06F11/1402 ,  G06F12/02 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3431

Abstract: A method of controlling a nonvolatile semiconductor memory including a plurality of blocks, each one of the plurality of blocks being a unit of data erasing, includes determining a monitored block as a candidate for refresh operation from among the plurality of blocks based on a predetermined condition. The method includes monitoring an error count of data stored in the monitored block and not monitoring an error count of data stored in blocks excluding the monitored block among the plurality of blocks. The method also includes performing the refresh operation on data stored in the monitored block in which the error count is larger than a first threshold value.

Abstract translation: 一种控制包括多个块的非易失性半导体存储器的方法，所述多个块中的每一个是数据擦除单元，包括：基于预定条件，将所监视的块作为所述多个块中的刷新操作的候补确定 。 该方法包括监视存储在所监视的块中的数据的错误计数，并且不监视存储在多个块中的被监视块之外的块中存储的数据的错误计数。 该方法还包括对存储在监视块中的数据执行刷新操作，其中错误计数大于第一阈值。

公开(公告)号：US20130179750A1

公开(公告)日：2013-07-11

申请号：US13820159

申请日：2011-12-15

Applicant: Toshikatsu Hida ,  Takashi Oshima ,  Kouji Watanabe

Inventor： Toshikatsu Hida ,  Takashi Oshima ,  Kouji Watanabe

IPC: G06F11/10

CPC classification number: G06F11/10 ,  G06F11/08 ,  G06F11/1004 ,  G06F11/1044 ,  G06F11/108 ,  G11C2029/0411 ,  H03M13/09 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/2906 ,  H03M13/2927 ,  H03M13/3723 ,  H04L67/1097

Abstract: According to one embodiment, a semiconductor storage device includes a nonvolatile semiconductor memory, a temporary storage buffer that temporarily stores writing data to be written to the nonvolatile semiconductor memory, and a coding processing unit that divides coding target data of an error correction code into two or more divided data and writes an error correction code obtained by performing an error correction coding process based on the divided data stored in the temporary storage buffer to the temporary storage buffer as an intermediate code.

Abstract translation: 根据一个实施例，半导体存储装置包括非易失性半导体存储器，临时存储要写入非易失性半导体存储器的写入数据的临时存储缓冲器，以及将纠错码的编码目标数据分成两部分的编码处理单元 或更多的分割数据，并将通过基于存储在临时存储缓冲器中的划分数据执行纠错编码处理而获得的纠错码写入临时存储缓冲器作为中间代码。

公开(公告)号：US20120311245A1

公开(公告)日：2012-12-06

申请号：US13571034

申请日：2012-08-09

Applicant: Hirokuni YANO ,  Shinichi Kanno ,  Toshikatsu Hida ,  Hidenori Matsuzaki ,  Kazuya Kitsunai ,  Shigehiro Asano

Inventor： Hirokuni YANO ,  Shinichi Kanno ,  Toshikatsu Hida ,  Hidenori Matsuzaki ,  Kazuya Kitsunai ,  Shigehiro Asano

IPC: G06F12/02

CPC classification number: G06F3/0604 ,  G06F3/0616 ,  G06F3/0631 ,  G06F3/064 ,  G06F3/0656 ,  G06F3/0658 ,  G06F3/0679 ,  G06F3/0685 ,  G06F12/0246 ,  G06F12/0804 ,  G06F12/0866 ,  G06F2212/7201 ,  G06F2212/7202 ,  G06F2212/7203 ,  G06F2212/7209 ,  G11C11/5628

Abstract: A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second and third memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data outputted from the first memory area by a first management unit in the second memory area, and a third processing for storing data outputted from the first memory area by a second management unit in the third memory area.

Abstract translation: 半导体存储装置包括配置在易失性半导体存储器中的第一存储区域，配置在非易失性半导体存储器中的第二和第三存储区域，以及执行以下处理的控制器。 控制器执行第一处理，用于通过第一存储区中的第一单元存储多个数据;第二处理，用于存储由第二存储区中的第一管理单元从第一存储区输出的数据;以及第三处理， 通过第二管理单元将从第一存储区域输出的数据存储在第三存储区域中。

公开(公告)号：US07953920B2

公开(公告)日：2011-05-31

申请号：US12552461

申请日：2009-09-02

Applicant: Hirokuni Yano ,  Shinichi Kanno ,  Toshikatsu Hida ,  Hidenori Matsuzaki ,  Kazuya Kitsunai ,  Shigehiro Asano

Inventor： Hirokuni Yano ,  Shinichi Kanno ,  Toshikatsu Hida ,  Hidenori Matsuzaki ,  Kazuya Kitsunai ,  Shigehiro Asano

IPC: G06F12/00

CPC classification number: G06F3/0604 ,  G06F3/0616 ,  G06F3/0631 ,  G06F3/064 ,  G06F3/0656 ,  G06F3/0658 ,  G06F3/0679 ,  G06F3/0685 ,  G06F12/0246 ,  G06F12/0804 ,  G06F12/0866 ,  G06F2212/7201 ,  G06F2212/7202 ,  G06F2212/7203 ,  G06F2212/7209 ,  G11C11/5628

Abstract: A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second, third and fourth memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data by a first management unit in the fourth memory area, a third processing for storing data by a second management unit in the third memory area, a fourth processing for moving an area of the third unit from the fourth memory area to the second memory area, a fifth processing for copying data to an area of the third unit and allocating the area to the second memory area, and a sixth processing for copying data to an empty area of the third unit in the second memory area.

Abstract translation: 半导体存储装置包括配置在非易失性半导体存储器中的易失性半导体存储器，第二，第三和第四存储区域中的第一存储区域和执行以下处理的控制器。 控制器执行第一处理，用于将第一单元存储在第一存储区域中的多个数据，第二处理，用于由第一管理单元存储在第四存储区域中的数据;第三处理，用于由第二管理单元存储数据 在第三存储区域中，用于将第三单元的区域从第四存储区域移动到第二存储区域的第四处理，用于将数据复制到第三单元的区域并将区域分配给第二存储区域的第五处理 以及用于将数据复制到第二存储区域中的第三单元的空白区域的第六处理。

公开(公告)号：US20110022784A1

公开(公告)日：2011-01-27

申请号：US12529139

申请日：2009-02-10

Applicant: Junji Yano ,  Kosuke Hatsuda ,  Hidenori Matsuzaki ,  Toshikatsu Hida

Inventor： Junji Yano ,  Kosuke Hatsuda ,  Hidenori Matsuzaki ,  Toshikatsu Hida

IPC: G06F12/00 ,  G06F12/02

CPC classification number: G06F12/0246 ,  G06F2212/7202 ,  G06F2212/7207 ,  G06F2212/7208 ,  G06F2212/7211

Abstract: A memory system according to an embodiment of the present invention comprises: a memory amount required for management table creation is reduced by adopting a nonvolatile semiconductor memory including a plurality of parallel operation elements respectively having a plurality of physical blocks as units of data erasing and a controller that can drive the parallel operation elements in parallel and has a number-of-times-of-erasing managing unit that manages the number of times of erasing in logical block units associated with a plurality of physical blocks driven in parallel.

Abstract translation: 根据本发明的实施例的存储器系统包括：通过采用包括分别具有多个物理块的多个并行操作元件作为数据擦除单元的非易失性半导体存储器来减少管理表创建所需的存储量，并且 控制器，其可以并行驱动并行操作元件，并且具有多个次数的擦除管理单元，其管理与并行驱动的多个物理块相关联的逻辑块单元中的擦除次数。

公开(公告)号：US20100169551A1

公开(公告)日：2010-07-01

申请号：US12563856

申请日：2009-09-21

Applicant: Hirokuni Yano ,  Toshikatsu Hida

Inventor： Hirokuni Yano ,  Toshikatsu Hida

IPC: G06F12/00 ,  G06F12/02 ,  G06F12/10

CPC classification number: G06F12/0246 ,  G06F2212/7201

Abstract: A forward lookup address translation table and a reverse lookup address translation table stored in a nonvolatile second storing unit are transferred as a master table to a volatile first storing unit at a time of start-up. When an event occurs so that the master table needs to be updated, difference information before and after update of any one of the forward lookup address translation table and the reverse lookup address translation table is recorded in the first storing unit as a log, thereby reducing an amount of the log.

Abstract translation: 存储在非易失性第二存储单元中的正向查找地址转换表和反向查找地址转换表在启动时被作为主表传送到易失性第一存储单元。 当发生事件以使主表需要更新时，在正向查找地址转换表和反向查找地址转换表中的任何一个更新之前和之后的差异信息作为日志记录在第一存储单元中，从而减少 一定量的日志。

公开(公告)号：US20100161885A1

公开(公告)日：2010-06-24

申请号：US12555274

申请日：2009-09-08

Applicant: Shinichi KANNO ,  Shigehiro Asano ,  Kazuya Kitsunai ,  Hirokuni Yano ,  Toshikatsu Hida

Inventor： Shinichi KANNO ,  Shigehiro Asano ,  Kazuya Kitsunai ,  Hirokuni Yano ,  Toshikatsu Hida

IPC: G06F12/00 ,  G06F12/02

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C16/105 ,  G11C2216/14

Abstract: A semiconductor storage device includes a first storage unit having a plurality of first blocks as data write regions; an instructing unit that issues a write instruction of writing data into the first blocks; a converting unit that converts an external address of input data to a memory position in the first block with reference to a conversion table in which external addresses of the data are associated with the memory positions of the data in the first blocks; and a judging unit that judges whether any of the first blocks store valid data associated with the external address based on the memory positions of the input data, wherein the instructing unit issues the write instruction of writing the data into the first block in which the valid data is not stored, when any of the first blocks does not store the valid data.

Abstract translation: 半导体存储装置包括具有作为数据写入区域的多个第一块的第一存储单元; 指示单元，其发出将数据写入到所述第一块中的写入指令; 转换单元，参照其中数据的外部地址与第一块中的数据的存储位置相关联的转换表，将输入数据的外部地址转换为第一块中的存储器位置; 以及判断单元，其基于所述输入数据的存储器位置判断所述第一块是否存储与所述外部地址相关联的有效数据，其中，所述指示单元发出将所述数据写入到所述第一块中的写入指令， 当任何第一个块不存储有效数据时，不存储数据。