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    SEMICONDUCTOR STORAGE DEVICE
    3.
    发明申请
    SEMICONDUCTOR STORAGE DEVICE 审中-公开
    半导体存储设备

    公开(公告)号：US20130191705A1

    公开(公告)日：2013-07-25

    申请号：US13824542

    申请日：2011-12-15

    Applicant: Kouji Watanabe ,  Toshikatsu Hida ,  Takashi Oshima

    Inventor： Kouji Watanabe ,  Toshikatsu Hida ,  Takashi Oshima

    IPC: G06F11/10

    CPC classification number: G06F11/1068 ,  G06F11/1056 ,  G11C2029/0411

    Abstract: According to an embodiment, a semiconductor storage device includes an error correction processing unit that executes encoding process related data to be dispersedly written over a plurality of memory areas and decoding process related data dispersedly written over the plurality of memory areas. A transfer management unit determines whether or not data related to the data transfer request is a target of the error correction process and causes the error correction processing unit to execute the error correction process only with respect to the data determined as the target of the error correction process.

    Abstract translation: 根据实施例，半导体存储装置包括错误校正处理单元，其执行要分散写入多个存储区域的编码处理相关数据，并解码分散写在多个存储区域上的处理相关数据。 传输管理单元确定与数据传输请求相关的数据是否是纠错处理的目标，并使纠错处理单元仅针对确定为纠错目标的数据执行纠错处理 处理。

    SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR CONTROLLING A SEMICONDUCTOR STORAGE DEVICE
    4.
    发明申请
    SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR CONTROLLING A SEMICONDUCTOR STORAGE DEVICE 审中-公开
    半导体存储器件和控制半导体存储器件的方法

    公开(公告)号：US20110239081A1

    公开(公告)日：2011-09-29

    申请号：US12887875

    申请日：2010-09-22

    Applicant: Toshikatsu Hida ,  Kouji Watanabe

    Inventor： Toshikatsu Hida ,  Kouji Watanabe

    IPC: H03M13/29 ,  G06F11/10

    CPC classification number: H03M13/2906 ,  G06F11/1012 ,  H03M13/09 ,  H03M13/1102 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/19 ,  H03M13/356 ,  H03M13/3715

    Abstract: According to one embodiment, write data is written in a nonvolatile semiconductor memory with a first error correction code and a second error correction code attached to the write data. The first error correction code and the write data are read out from the nonvolatile semiconductor memory to perform first error correction processing. When there is a remaining error, the second error correction code corresponding to the write data is read out to carry out second error correction processing.

    Abstract translation: 根据一个实施例，写入数据被写入非易失性半导体存储器中，其中第一纠错码和附加到写数据的第二纠错码。 从非易失性半导体存储器读出第一纠错码和写入数据，进行第一纠错处理。 当存在剩余错误时，读出与写入数据相对应的第二纠错码，以进行第二纠错处理。

    Memory system including first and second caches and controlling readout of data therefrom
    5.
    发明授权
    Memory system including first and second caches and controlling readout of data therefrom 有权

    公开(公告)号：US08732397B2

    公开(公告)日：2014-05-20

    申请号：US13326929

    申请日：2011-12-15

    Applicant: Toshikatsu Hida ,  Norikazu Yoshida ,  Kouji Watanabe

    Inventor： Toshikatsu Hida ,  Norikazu Yoshida ,  Kouji Watanabe

    IPC: G06F12/08 ,  G06F12/02 ,  G06F3/06

    Abstract: According to one embodiment, a memory system includes a chip including a cell array and first and second caches configured to hold data read out from the cell array; an interface configured to manage a first and a second addresses; a controller configured to issue a readout request to the interface; and a buffer configured to hold the data from the chip. The interface transfers the data in the first cache to the buffer without reading out the data from the cell array if the readout address matches the first address, transfers the data in the second cache to the buffer without reading out the data from the cell array if the readout address matches the second address, and reads out the data from the cell array and transfers the data to the buffer if the readout address does not match either one of the first or second address.

    Memory system including first and second caches and controlling readout of data therefrom
    6.
    发明授权
    Memory system including first and second caches and controlling readout of data therefrom 有权
    存储器系统包括第一和第二高速缓存，并控制数据的读出

    公开(公告)号：US08775739B2

    公开(公告)日：2014-07-08

    申请号：US13326929

    申请日：2011-12-15

    Applicant: Toshikatsu Hida ,  Norikazu Yoshida ,  Kouji Watanabe

    Inventor： Toshikatsu Hida ,  Norikazu Yoshida ,  Kouji Watanabe

    IPC: G06F12/08 ,  G06F12/02 ,  G06F3/06

    CPC classification number: G06F12/0862 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2212/7203 ,  G06F2212/7208

    Abstract: According to one embodiment, a memory system includes a chip including a cell array and first and second caches configured to hold data read out from the cell array; an interface configured to manage a first and a second addresses; a controller configured to issue a readout request to the interface; and a buffer configured to hold the data from the chip. The interface transfers the data in the first cache to the buffer without reading out the data from the cell array if the readout address matches the first address, transfers the data in the second cache to the buffer without reading out the data from the cell array if the readout address matches the second address, and reads out the data from the cell array and transfers the data to the buffer if the readout address does not match either one of the first or second address.

    Abstract translation: 根据一个实施例，存储器系统包括：芯片，其包括单元阵列;第一和第二高速缓存，被配置为保存从单元阵列读出的数据; 被配置为管理第一和第二地址的接口; 控制器，被配置为向所述接口发出读出请求; 以及被配置为保存来自芯片的数据的缓冲器。 如果读出地址匹配第一个地址，则接口将第一个高速缓存中的数据传输到缓冲区，而不会从单元阵列中读出数据，将第二个高速缓存中的数据传输到缓冲区，而不从单元阵​​列中读出数据，如果 读出地址与第二个地址匹配，并从单元阵列中读出数据，如果读出地址与第一个或第二个地址中的任何一个不匹配，则将数据传送到缓冲区。

    MEMORY SYSTEM
    7.
    发明申请
    MEMORY SYSTEM 有权
    记忆系统

    公开(公告)号：US20120159072A1

    公开(公告)日：2012-06-21

    申请号：US13326929

    申请日：2011-12-15

    Applicant: Toshikatsu Hida ,  Norikazu Yoshida ,  Kouji Watanabe

    Inventor： Toshikatsu Hida ,  Norikazu Yoshida ,  Kouji Watanabe

    IPC: G06F12/08

    CPC classification number: G06F12/0862 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2212/7203 ,  G06F2212/7208

    Abstract: According to one embodiment, a memory system includes a chip including a cell array and first and second caches configured to hold data read out from the cell array; an interface configured to manage a first and a second addresses; a controller configured to issue a readout request to the interface; and a buffer configured to hold the data from the chip. The interface transfers the data in the first cache to the buffer without reading out the data from the cell array if the readout address matches the first address, transfers the data in the second cache to the buffer without reading out the data from the cell array if the readout address matches the second address, and reads out the data from the cell array and transfers the data to the buffer if the readout address does not match either one of the first or second address.

    Abstract translation: 根据一个实施例，存储器系统包括：芯片，其包括单元阵列;第一和第二高速缓存，被配置为保存从单元阵列读出的数据; 被配置为管理第一和第二地址的接口; 控制器，被配置为向所述接口发出读出请求; 以及被配置为保存来自芯片的数据的缓冲器。 如果读出地址匹配第一个地址，则接口将第一个高速缓存中的数据传输到缓冲区，而不会从单元阵列中读出数据，将第二个高速缓存中的数据传输到缓冲区，而不从单元阵​​列中读出数据，如果 读出地址与第二个地址匹配，并从单元阵列中读出数据，如果读出地址与第一个或第二个地址中的任何一个不匹配，则将数据传送到缓冲区。

    Encoding apparatus, control method of encoding apparatus, and memory device
    8.
    发明授权
    Encoding apparatus, control method of encoding apparatus, and memory device 有权
    编码装置，编码装置的控制方法和存储装置

    公开(公告)号：US09331713B2

    公开(公告)日：2016-05-03

    申请号：US13600929

    申请日：2012-08-31

    Applicant: Yoshiki Saito ,  Shinichi Kanno ,  Toshikatsu Hida

    Inventor： Yoshiki Saito ,  Shinichi Kanno ,  Toshikatsu Hida

    IPC: H03M13/05 ,  H03M13/00

    CPC classification number: H03M13/05 ,  H03M13/6516

    Abstract: According to an embodiment, an encoding apparatus includes a parameter holding unit configured to hold a parameter; an error-detecting code holding unit configured to hold an error-detecting code that is generated from the parameter; an error detecting unit configured to detect an error in the parameter, which is held in the parameter holding unit, with the use of the error-detecting code held in the error-detecting code holding unit; an error correcting unit configured to correct the error detected by the error detecting unit; a selecting unit configured to select the parameter that has been subjected to error correction by the error correcting unit; and an encoding unit configured to encode data with the use of the parameter selected by the selecting unit.

    Abstract translation: 根据实施例，一种编码装置包括：配置为保存参数的参数保持单元; 错误检测码保持单元，被配置为保存从该参数生成的检错码; 错误检测单元，被配置为使用保持在错误检测码保持单元中的检错码来检测保存在参数保持单元中的参数中的错误; 错误校正单元，被配置为校正由所述错误检测单元检测到的所述错误; 选择单元，被配置为通过误差校正单元选择已经经过纠错的参数; 以及编码单元，被配置为使用由所述选择单元选择的参数来对数据进行编码。

    Method of controlling a semiconductor storage device
    10.
    发明授权
    Method of controlling a semiconductor storage device 有权
    控制半导体存储装置的方法

    公开(公告)号：US08583972B2

    公开(公告)日：2013-11-12

    申请号：US13486718

    申请日：2012-06-01

    Applicant: Toshikatsu Hida ,  Shinichi Kanno ,  Hirokuni Yano ,  Kazuya Kitsunai ,  Shigehiro Asano ,  Junji Yano

    Inventor： Toshikatsu Hida ,  Shinichi Kanno ,  Hirokuni Yano ,  Kazuya Kitsunai ,  Shigehiro Asano ,  Junji Yano

    IPC: G11C29/00

    CPC classification number: G06F11/1412 ,  G06F11/1068 ,  G06F11/1402 ,  G06F12/02 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3431

    Abstract: A method of controlling a nonvolatile semiconductor memory including a plurality of blocks, each one of the plurality of blocks being a unit of data erasing, includes determining a monitored block as a candidate for refresh operation from among the plurality of blocks based on a predetermined condition. The method includes monitoring an error count of data stored in the monitored block and not monitoring an error count of data stored in blocks excluding the monitored block among the plurality of blocks. The method also includes performing the refresh operation on data stored in the monitored block in which the error count is larger than a first threshold value.

    Abstract translation: 一种控制包括多个块的非易失性半导体存储器的方法，所述多个块中的每一个是数据擦除单元，包括：基于预定条件，将所监视的块作为所述多个块中的刷新操作的候补确定 。 该方法包括监视存储在所监视的块中的数据的错误计数，并且不监视存储在多个块中的被监视块之外的块中存储的数据的错误计数。 该方法还包括对存储在监视块中的数据执行刷新操作，其中错误计数大于第一阈值。

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