公开(公告)号：US12112987B2

公开(公告)日：2024-10-08

申请号：US18226185

申请日：2023-07-25

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Tzu-Chung Wang ,  Tung Ying Lee

IPC分类号： H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L21/823468 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/6681 ,  H01L29/785

摘要： A semiconductor device includes a plurality of fins on a substrate, a fin end spacer plug on an end surface of each of the plurality of fins and a fin liner layer, an insulating layer on the plurality of fins, and a source/drain epitaxial layer in a source/drain recess in each of the plurality of fins.

公开(公告)号：US11955547B2

公开(公告)日：2024-04-09

申请号：US16227107

申请日：2018-12-20

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Te-Jen Pan ,  Yu-Hsien Lin ,  Hsiang-Ku Shen ,  Wei-Han Fan ,  Yun Jing Lin ,  Yimin Huang ,  Tzu-Chung Wang

IPC分类号： H01L29/78 ,  H01L21/8238 ,  H01L29/04 ,  H01L29/06 ,  H01L29/165 ,  H01L29/66

CPC分类号： H01L29/7833 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823864 ,  H01L21/823871 ,  H01L29/04 ,  H01L29/0649 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： An integrated circuit device includes a gate stack disposed over a substrate. A first L-shaped spacer is disposed along a first sidewall of the gate stack and a second L-shaped spacer is disposed along a second sidewall of the gate stack. The first L-shaped spacer and the second L-shaped spacer include silicon and carbon. A first source/drain epitaxy region and a second source/drain epitaxy region are disposed over the substrate. The gate stack is disposed between the first source/drain epitaxy region and the second source/drain epitaxy region. An interlevel dielectric (ILD) layer disposed over the substrate. The ILD layer is disposed between the first source/drain epitaxy region and a portion of the first L-shaped spacer disposed along the first sidewall of the gate stack and between the second source/drain epitaxy region and a portion of the second L-shaped spacer disposed along the second sidewall of the gate stack.

公开(公告)号：US11817488B2

公开(公告)日：2023-11-14

申请号：US17341676

申请日：2021-06-08

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Tung Ying Lee ,  Shao-Ming Yu ,  Tzu-Chung Wang

IPC分类号： H01L29/78 ,  H01L29/423 ,  H01L29/51 ,  H01L21/28 ,  H01L29/66 ,  H10B61/00

CPC分类号： H01L29/42364 ,  H01L21/28158 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66492 ,  H01L29/66545 ,  H01L29/7833 ,  H10B61/22

摘要： In some embodiments, a method for forming an integrated chip (IC) is provided. The method incudes forming an interlayer dielectric (ILD) layer over a substrate. A first opening is formed in the ILD layer and in a first region of the IC. A second opening is formed in the ILD layer and in a second region of the IC. A first high-k dielectric layer is formed lining both the first and second openings. A second dielectric layer is formed on the first high-k dielectric layer and lining the first high-k dielectric layer in both the first and second regions. The second high-k dielectric layer is removed from the first region. A conductive layer is formed over both the first and second high-k dielectric layers, where the conductive layer contacts the first high-k dielectric layer in the first region and contacts the second high-k dielectric in the second region.

公开(公告)号：US10164093B2

公开(公告)日：2018-12-25

申请号：US15457613

申请日：2017-03-13

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Te-Jen Pan ,  Yu-Hsien Lin ,  Hsiang-Ku Shen ,  Wei-Han Fan ,  Yun Jing Lin ,  Yimin Huang ,  Tzu-Chung Wang

IPC分类号： H01L29/76 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/165 ,  H01L29/66 ,  H01L29/04 ,  H01L29/06

摘要： An exemplary method includes forming a dummy gate structure over a substrate and forming a set of spacers adjacent to the dummy gate structure. The set of spacers includes spacer liners disposed on sidewalls of the dummy gate structure and main spacers disposed on the spacer liners. The spacer liners include silicon and carbon. The method further includes forming source/drain epitaxy regions over the substrate. The source/drain epitaxy regions are disposed adjacent to the set of spacers, such that the dummy gate structure is disposed between the source/drain epitaxy regions. The method further includes removing the main spacers after forming the source/drain epitaxy regions. The method further includes replacing the dummy gate structure with a gate structure, where the replacing includes removing the dummy gate structure to form a trench defined by the spacers liners, such that the gate structure is formed in the trench.

公开(公告)号：US20210296461A1

公开(公告)日：2021-09-23

申请号：US17341676

申请日：2021-06-08

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Tung Ying Lee ,  Shao-Ming Yu ,  Tzu-Chung Wang

IPC分类号： H01L29/423 ,  H01L27/22 ,  H01L29/51 ,  H01L21/28 ,  H01L29/78 ,  H01L29/66

摘要： In some embodiments, a method for forming an integrated chip (IC) is provided. The method incudes forming an interlayer dielectric (ILD) layer over a substrate. A first opening is formed in the ILD layer and in a first region of the IC. A second opening is formed in the ILD layer and in a second region of the IC. A first high-k dielectric layer is formed lining both the first and second openings. A second dielectric layer is formed on the first high-k dielectric layer and lining the first high-k dielectric layer in both the first and second regions. The second high-k dielectric layer is removed from the first region. A conductive layer is formed over both the first and second high-k dielectric layers, where the conductive layer contacts the first high-k dielectric layer in the first region and contacts the second high-k dielectric in the second region.

公开(公告)号：US20240021692A1

公开(公告)日：2024-01-18

申请号：US18364011

申请日：2023-08-02

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Tung Ying Lee ,  Shao-Ming Yu ,  Tzu-Chung Wang

IPC分类号： H01L29/423 ,  H01L29/51 ,  H01L21/28 ,  H01L29/78 ,  H01L29/66 ,  H10B61/00

CPC分类号： H01L29/42364 ,  H01L29/513 ,  H01L21/28158 ,  H01L29/7833 ,  H01L29/66492 ,  H01L29/66545 ,  H01L29/517 ,  H10B61/22

摘要： In some embodiments, a method for forming an integrated chip (IC) is provided. The method incudes forming an interlayer dielectric (ILD) layer over a substrate. A first opening is formed in the ILD layer and in a first region of the IC. A second opening is formed in the ILD layer and in a second region of the IC. A first high-k dielectric layer is formed lining both the first and second openings. A second dielectric layer is formed on the first high-k dielectric layer and lining the first high-k dielectric layer in both the first and second regions. The second high-k dielectric layer is removed from the first region. A conductive layer is formed over both the first and second high-k dielectric layers, where the conductive layer contacts the first high-k dielectric layer in the first region and contacts the second high-k dielectric in the second region.

公开(公告)号：US11798849B2

公开(公告)日：2023-10-24

申请号：US17591906

申请日：2022-02-03

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Tzu-Chung Wang ,  Tung Ying Lee

IPC分类号： H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L27/088

CPC分类号： H01L21/823468 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/6681 ,  H01L29/785

摘要： A semiconductor device includes a plurality of fins on a substrate, a fin end spacer plug on an end surface of each of the plurality of fins and a fin liner layer, an insulating layer on the plurality of fins, and a source/drain epitaxial layer in a source/drain recess in each of the plurality of fins.

公开(公告)号：US11721700B2

公开(公告)日：2023-08-08

申请号：US17355395

申请日：2021-06-23

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shih-Yao Lin ,  Chih-Han Lin ,  Ming-Ching Chang ,  Shu-Yuan Ku ,  Tzu-Chung Wang

IPC分类号： H01L27/092 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L27/0924 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/6681 ,  H01L29/7851

摘要： A semiconductor device includes a substrate. The semiconductor device includes a dielectric fin that is formed over the substrate and extends along a first direction. The semiconductor device includes a gate isolation structure vertically disposed above the dielectric fin. The semiconductor device includes a gate structure extending along a second direction perpendicular to the first direction. The gate structure includes a first portion and a second portion separated by the gate isolation structure and the dielectric fin. The first portion of the gate structure presents a first beak profile and the second portion of the gate structure presents a second beak profile. The first and second beak profiles point toward each other.

公开(公告)号：US11626510B2

公开(公告)日：2023-04-11

申请号：US17582729

申请日：2022-01-24

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shih-Yao Lin ,  Chih-Han Lin ,  Shu-Uei Jang ,  Ya-Yi Tsai ,  Chi-Hsiang Chang ,  Tzu-Chung Wang ,  Shu-Yuan Ku

IPC分类号： H01L31/119 ,  H01L29/76 ,  H01L29/94 ,  H01L29/66 ,  H01L29/417 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/78

摘要： A method includes forming a first fin and a second fin over a substrate. The method includes forming a first dummy gate structure that straddles the first fin and the second fin. The first dummy gate structure includes a first dummy gate dielectric and a first dummy gate disposed over the first dummy gate dielectric. The method includes replacing a portion of the first dummy gate with a gate isolation structure. The portion of the first dummy gate is disposed over the second fin. The method includes removing the first dummy gate. The method includes removing a first portion of the first dummy gate dielectric around the first fin, while leaving a second portion of the first dummy gate dielectric around the second fin intact. The method includes forming a gate feature straddling the first fin and the second fin, wherein the gate isolation structure intersects the gate feature.

公开(公告)号：US20220415889A1

公开(公告)日：2022-12-29

申请号：US17355395

申请日：2021-06-23

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shih-Yao Lin ,  Chih-Han Lin ,  Ming-Ching Chang ,  Shu-Yuan Ku ,  Tzu-Chung Wang

IPC分类号： H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L21/8234

摘要： A semiconductor device includes a substrate. The semiconductor device includes a dielectric fin that is formed over the substrate and extends along a first direction. The semiconductor device includes a gate isolation structure vertically disposed above the dielectric fin. The semiconductor device includes a gate structure extending along a second direction perpendicular to the first direction. The gate structure includes a first portion and a second portion separated by the gate isolation structure and the dielectric fin. The first portion of the gate structure presents a first beak profile and the second portion of the gate structure presents a second beak profile. The first and second beak profiles point toward each other.