公开(公告)号：US20250056832A1

公开(公告)日：2025-02-13

申请号：US18932253

申请日：2024-10-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Cheng-Lung Hung ,  Weng Chang ,  Chi On Chui

IPC: H01L29/417 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78

Abstract: Methods for tuning effective work functions of gate electrodes in semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a channel region over a semiconductor substrate; a gate dielectric layer over the channel region; and a gate electrode over the gate dielectric layer, the gate electrode including a first work function metal layer over the gate dielectric layer, the first work function metal layer including aluminum (Al); a first work function tuning layer over the first work function metal layer, the first work function tuning layer including aluminum tungsten (AIW); and a fill material over the first work function tuning layer.

公开(公告)号：US12166095B2

公开(公告)日：2024-12-10

申请号：US18525521

申请日：2023-11-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Cheng-Lung Hung ,  Weng Chang ,  Chi On Chui

IPC: H01L29/417 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78

Abstract: Methods for tuning effective work functions of gate electrodes in semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a channel region over a semiconductor substrate; a gate dielectric layer over the channel region; and a gate electrode over the gate dielectric layer, the gate electrode including a first work function metal layer over the gate dielectric layer, the first work function metal layer including aluminum (Al); a first work function tuning layer over the first work function metal layer, the first work function tuning layer including aluminum tungsten (AlW); and a fill material over the first work function tuning layer.

公开(公告)号：US20240379809A1

公开(公告)日：2024-11-14

申请号：US18782219

申请日：2024-07-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Weng Chang ,  Chi On Chui

IPC: H01L29/49 ,  H01L21/02 ,  H01L21/28 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: In an embodiment, a device includes: a p-type transistor including: a first channel region; a first gate dielectric layer on the first channel region; a tungsten-containing work function tuning layer on the first gate dielectric layer; and a first fill layer on the tungsten-containing work function tuning layer; and an n-type transistor including: a second channel region; a second gate dielectric layer on the second channel region; a tungsten-free work function tuning layer on the second gate dielectric layer; and a second fill layer on the tungsten-free work function tuning layer.

公开(公告)号：US20240371973A1

公开(公告)日：2024-11-07

申请号：US18773070

申请日：2024-07-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Peng-Soon Lim ,  Cheng-Lung Hung ,  Mao-Lin Huang ,  Weng Chang

IPC: H01L29/66 ,  H01L21/28 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78

Abstract: A method includes forming a dummy gate stack, forming a dielectric layer, with the dummy gate stack located in the dielectric layer, removing the dummy gate stack to form a opening in the dielectric layer, forming a metal layer extending into the opening, and etching back the metal layer. The remaining portions of the metal layer in the opening have edges lower than a top surface of the dielectric layer. A conductive layer is selectively deposited in the opening. The conductive layer is over the metal layer, and the metal layer and the conductive layer in combination form a replacement gate.

公开(公告)号：US12068393B2

公开(公告)日：2024-08-20

申请号：US17663979

申请日：2022-05-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Peng-Soon Lim ,  Cheng-Lung Hung ,  Mao-Lin Huang ,  Weng Chang

IPC: H01L29/66 ,  H01L21/28 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L29/06 ,  H01L29/51

CPC classification number: H01L29/66545 ,  H01L21/28026 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/66583 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/0673 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66439 ,  H01L29/665

Abstract: A method includes forming a dummy gate stack, forming a dielectric layer, with the dummy gate stack located in the dielectric layer, removing the dummy gate stack to form a opening in the dielectric layer, forming a metal layer extending into the opening, and etching back the metal layer. The remaining portions of the metal layer in the opening have edges lower than a top surface of the dielectric layer. A conductive layer is selectively deposited in the opening. The conductive layer is over the metal layer, and the metal layer and the conductive layer in combination form a replacement gate.

公开(公告)号：US12051721B2

公开(公告)日：2024-07-30

申请号：US17813980

申请日：2022-07-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Ji-Cheng Chen ,  Cheng-Lung Hung ,  Weng Chang ,  Chi On Chui

IPC: H01L29/06 ,  H01L21/02 ,  H01L29/423 ,  H01L29/49

CPC classification number: H01L29/0673 ,  H01L21/02178 ,  H01L21/02186 ,  H01L21/0245 ,  H01L21/02458 ,  H01L21/0262 ,  H01L29/0638 ,  H01L29/0676 ,  H01L29/42392 ,  H01L29/4925 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/4975

Abstract: A semiconductor device including a barrier layer surrounding a work function metal layer and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a semiconductor substrate; a first channel region over the semiconductor substrate; a second channel region over the first channel region; gate dielectric layers surrounding the first channel region and the second channel region; work function metal layers surrounding the gate dielectric layers; and barrier layers surrounding the work function metal layers, a first barrier layer surrounding the first channel region being merged with a second barrier layer surrounding the second channel region.

公开(公告)号：US20240153952A1

公开(公告)日：2024-05-09

申请号：US18404606

申请日：2024-01-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Weng Chang ,  Chi On Chui

IPC: H01L27/092 ,  H01L21/02 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L21/0228 ,  H01L29/0665 ,  H01L29/66795 ,  H01L29/7851

Abstract: In an embodiment, a device includes: a channel region; a gate dielectric layer on the channel region; a first work function tuning layer on the gate dielectric layer, the first work function tuning layer including a n-type work function metal; a barrier layer on the first work function tuning layer; a second work function tuning layer on the barrier layer, the second work function tuning layer including a p-type work function metal, the p-type work function metal different from the n-type work function metal; and a fill layer on the second work function tuning layer.

公开(公告)号：US20230335551A1

公开(公告)日：2023-10-19

申请号：US17896970

申请日：2022-08-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yao-Teng Chuang ,  Kuei-Lun Lin ,  Te-Yang Lai ,  Da-Yuan Lee ,  Weng Chang ,  Chi On Chui

IPC: H01L27/088 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/823431

Abstract: Semiconductor devices and methods of manufacturing semiconductor devices with differing threshold voltages are provided. In embodiments the threshold voltages of individual semiconductor devices are tuned through the deposition, diffusion, and removal of dipole materials in order to provide different dipole regions within different transistors. These different dipole regions cause the different transistors to have different threshold voltages.

公开(公告)号：US20230317859A1

公开(公告)日：2023-10-05

申请号：US17833348

申请日：2022-06-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Weng Chang ,  Chi On Chui

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L29/78696 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/0669

Abstract: A device includes a semiconductor substrate; a vertically stacked set of nanostructures over the semiconductor substrate; a first source/drain region; and a second source/drain region, wherein the vertically stacked set of nanostructures extends between the first source/drain region and the second source/drain region along a first cross-section. The device further includes a gate structure encasing the vertically stacked set of nanostructures along a second cross-section. The second cross-section is along a longitudinal axis of the gate structure. The gate structure comprises: a gate dielectric encasing each of the vertically stacked set of nanostructures; a first metal carbide layer over the gate dielectric; and a gate fill material over the first metal carbide layer. The first metal carbide layer comprises Ce, Hf, V, Nb, Sc, Y, or
Mo.

公开(公告)号：US20230073400A1

公开(公告)日：2023-03-09

申请号：US17986379

申请日：2022-11-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Yen Tsai ,  Ming-Chi Huang ,  Zoe Chen ,  Wei-Chin Lee ,  Cheng-Lung Hung ,  Da-Yuan Lee ,  Weng Chang ,  Ching-Hwanq Su

IPC: H01L27/092 ,  H01L21/324 ,  H01L29/66 ,  H01L29/51 ,  H01L29/78 ,  H01L29/08 ,  H01L21/768 ,  H01L21/28 ,  H01L21/8238 ,  H01L21/02 ,  H01L29/10 ,  H01L21/321 ,  H01L21/027

Abstract: In an embodiment, a method includes: forming a gate dielectric layer on an interface layer; forming a doping layer on the gate dielectric layer, the doping layer including a dipole-inducing element; annealing the doping layer to drive the dipole-inducing element through the gate dielectric layer to a first side of the gate dielectric layer adjacent the interface layer; removing the doping layer; forming a sacrificial layer on the gate dielectric layer, a material of the sacrificial layer reacting with residual dipole-inducing elements at a second side of the gate dielectric layer adjacent the sacrificial layer; removing the sacrificial layer; forming a capping layer on the gate dielectric layer; and forming a gate electrode layer on the capping layer.