公开(公告)号：US20210375776A1

公开(公告)日：2021-12-02

申请号：US17017356

申请日：2020-09-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Chen Ho ,  Chien Lin ,  Cheng-Yeh Yu ,  Hsin-Hsing Chen ,  Ju Ru Hsieh

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/522

Abstract: The present disclosure provides a structure and a method to reduce electro-migration. An interconnect structure according to the present disclosure includes a conductive feature embedded in a dielectric layer, a capping barrier layer disposed over the conductive feature and the dielectric layer, and an adhesion layer sandwiched between the capping barrier layer and the dielectric layer. The adhesion layer includes a degree of crystallinity between about 40% and about 70%.

公开(公告)号：US10950426B2

公开(公告)日：2021-03-16

申请号：US16103744

申请日：2018-08-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Chen Ho ,  You-Hua Chou ,  Yen-Hao Liao ,  Che-Lun Chang ,  Zhen-Cheng Wu

IPC: H01L21/02 ,  H01L21/768 ,  H01L21/311

Abstract: A method for manufacturing a dielectric layer includes forming a first dielectric film over a substrate. A first porogen is deposited over the first dielectric film. A second dielectric film is formed on and in contact with the first dielectric film and the first porogen. The first porogen is removed.

公开(公告)号：US12014919B2

公开(公告)日：2024-06-18

申请号：US17199066

申请日：2021-03-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Chen Ho ,  You-Hua Chou ,  Yen-Hao Liao ,  Che-Lun Chang ,  Zhen-Cheng Wu

IPC: H01L21/02 ,  H01L21/311 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L21/02203 ,  H01L21/0228 ,  H01L21/31138 ,  H01L21/7682 ,  H01L23/5329 ,  H01L23/53295 ,  H01L21/02118 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/02299 ,  H01L21/76807 ,  H01L21/76835 ,  H01L21/76843 ,  H01L21/76877

Abstract: A structure includes a first dielectric film and a second dielectric film. The second dielectric film is formed on and in contact with the first dielectric film, in which a first pore is formed between the first dielectric film and the second dielectric film, and a thickness of the first dielectric film is smaller than a diameter of the first pore.

公开(公告)号：US12068317B2

公开(公告)日：2024-08-20

申请号：US17727620

申请日：2022-04-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Chen Ho ,  Chien Lin ,  Tzu-Wei Lin ,  Ju Ru Hsieh ,  Ching-Lun Lai ,  Ming-Kai Lo

IPC: H01L27/08 ,  H01L27/088 ,  H01L27/092 ,  H10B12/00

CPC classification number: H01L27/0886 ,  H01L27/0924 ,  H10B12/36

Abstract: An integrated circuit die includes a FinFET transistor. The FinFET transistor includes an anti-punch through region below a channel region. Undesirable dopants are removed from the anti-punch through region during formation of the source and drain regions. When source and drain recesses are formed, a layer of dielectric material is deposited in the recesses. An annealing process is then performed. Undesirable dopants diffuse from the anti-punch through region into the layer of dielectric material during the annealing process. The layer of dielectric material is then removed. The source and drain regions are then formed by depositing semiconductor material in the recesses.

公开(公告)号：US12014987B2

公开(公告)日：2024-06-18

申请号：US17869012

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Chen Ho ,  Chien Lin ,  Cheng-Yeh Yu ,  Hsin-Hsing Chen ,  Ju Ru Hsieh

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/53238 ,  H01L21/76834 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76871 ,  H01L23/5226

Abstract: The present disclosure provides a structure and a method to reduce electro-migration. An interconnect structure according to the present disclosure includes a conductive feature embedded in a dielectric layer, a capping barrier layer disposed over the conductive feature and the dielectric layer, and an adhesion layer sandwiched between the capping barrier layer and the dielectric layer. The adhesion layer includes a degree of crystallinity between about 40% and about 70%.

公开(公告)号：US11450609B2

公开(公告)日：2022-09-20

申请号：US17017356

申请日：2020-09-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Chen Ho ,  Chien Lin ,  Cheng-Yeh Yu ,  Hsin-Hsing Chen ,  Ju Ru Hsieh

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/522

Abstract: The present disclosure provides a structure and a method to reduce electro-migration. An interconnect structure according to the present disclosure includes a conductive feature embedded in a dielectric layer, a capping barrier layer disposed over the conductive feature and the dielectric layer, and an adhesion layer sandwiched between the capping barrier layer and the dielectric layer. The adhesion layer includes a degree of crystallinity between about 40% and about 70%.

公开(公告)号：US11164937B2

公开(公告)日：2021-11-02

申请号：US16255567

申请日：2019-01-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Chen Ho ,  Chien Lin ,  You-Hua Chou ,  Hsing-Yuan Huang ,  Cheng-Yu Hung

IPC: H01L49/02 ,  H01L21/02 ,  H01L21/321 ,  H01L21/311

Abstract: A semiconductor device includes a semiconductor substrate, a capacitor, and an interconnection layer. The capacitor is over the semiconductor substrate and includes a bottom electrode, a top electrode, and an insulator layer. The top electrode has a top surface and a bottom surface rougher than the top surface of the top electrode. The insulator layer is between the bottom electrode and the top electrode. The interconnection layer is over the semiconductor substrate and is electrically connected to the capacitor.

公开(公告)号：US20240332190A1

公开(公告)日：2024-10-03

申请号：US18740705

申请日：2024-06-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Chen Ho ,  Chien Lin ,  Cheng-Yeh Yu ,  Hsin-Hsing Chen ,  Ju Ru Hsieh

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/53238 ,  H01L21/76834 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76871 ,  H01L23/5226

Abstract: The present disclosure provides a structure and a method to reduce electro-migration. An interconnect structure according to the present disclosure includes a conductive feature embedded in a dielectric layer, a capping barrier layer disposed over the conductive feature and the dielectric layer, and an adhesion layer sandwiched between the capping barrier layer and the dielectric layer. The adhesion layer includes a degree of crystallinity between about 40% and about 70%.

公开(公告)号：US11721694B2

公开(公告)日：2023-08-08

申请号：US16803965

申请日：2020-02-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Chen Ho ,  Hung Chih Hu ,  Hung Cheng Yu ,  Ju Ru Hsieh

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/06

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823878 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/0649

Abstract: A semiconductor device including fin field-effect transistors, includes a first gate structure extending in a first direction, a second gate structure extending the first direction and aligned with the first gate structure in the first direction, a third gate structure extending in the first direction and arranged in parallel with the first gate structure in a second direction crossing the first direction, a fourth gate structure extending the first direction, aligned with the third gate structure and arranged in parallel with the second gate structure, an interlayer dielectric layer disposed between the first to fourth gate electrodes, and a separation wall made of different material than the interlayer dielectric layer and disposed between the first and third gate structures and the second and fourth gate structures.

公开(公告)号：US11315921B2

公开(公告)日：2022-04-26

申请号：US16721640

申请日：2019-12-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Chen Ho ,  Chien Lin ,  Tzu-Wei Lin ,  Ju Ru Hsieh ,  Ching-Lun Lai ,  Ming-Kai Lo

IPC: H01L27/08 ,  H01L27/088 ,  H01L27/108 ,  H01L27/092

Abstract: An integrated circuit die includes a FinFET transistor. The FinFET transistor includes an anti-punch through region below a channel region. Undesirable dopants are removed from the anti-punch through region during formation of the source and drain regions. When source and drain recesses are formed, a layer of dielectric material is deposited in the recesses. An annealing process is then performed. Undesirable dopants diffuse from the anti-punch through region into the layer of dielectric material during the annealing process. The layer of dielectric material is then removed. The source and drain regions are then formed by depositing semiconductor material in the recesses.