公开(公告)号：US12014987B2

公开(公告)日：2024-06-18

申请号：US17869012

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Chen Ho ,  Chien Lin ,  Cheng-Yeh Yu ,  Hsin-Hsing Chen ,  Ju Ru Hsieh

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/53238 ,  H01L21/76834 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76871 ,  H01L23/5226

Abstract: The present disclosure provides a structure and a method to reduce electro-migration. An interconnect structure according to the present disclosure includes a conductive feature embedded in a dielectric layer, a capping barrier layer disposed over the conductive feature and the dielectric layer, and an adhesion layer sandwiched between the capping barrier layer and the dielectric layer. The adhesion layer includes a degree of crystallinity between about 40% and about 70%.

公开(公告)号：US11450609B2

公开(公告)日：2022-09-20

申请号：US17017356

申请日：2020-09-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Chen Ho ,  Chien Lin ,  Cheng-Yeh Yu ,  Hsin-Hsing Chen ,  Ju Ru Hsieh

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/522

Abstract: The present disclosure provides a structure and a method to reduce electro-migration. An interconnect structure according to the present disclosure includes a conductive feature embedded in a dielectric layer, a capping barrier layer disposed over the conductive feature and the dielectric layer, and an adhesion layer sandwiched between the capping barrier layer and the dielectric layer. The adhesion layer includes a degree of crystallinity between about 40% and about 70%.

公开(公告)号：US20210375776A1

公开(公告)日：2021-12-02

申请号：US17017356

申请日：2020-09-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Chen Ho ,  Chien Lin ,  Cheng-Yeh Yu ,  Hsin-Hsing Chen ,  Ju Ru Hsieh

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/522

Abstract: The present disclosure provides a structure and a method to reduce electro-migration. An interconnect structure according to the present disclosure includes a conductive feature embedded in a dielectric layer, a capping barrier layer disposed over the conductive feature and the dielectric layer, and an adhesion layer sandwiched between the capping barrier layer and the dielectric layer. The adhesion layer includes a degree of crystallinity between about 40% and about 70%.

公开(公告)号：US20240332190A1

公开(公告)日：2024-10-03

申请号：US18740705

申请日：2024-06-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Chen Ho ,  Chien Lin ,  Cheng-Yeh Yu ,  Hsin-Hsing Chen ,  Ju Ru Hsieh

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/53238 ,  H01L21/76834 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76871 ,  H01L23/5226

Abstract: The present disclosure provides a structure and a method to reduce electro-migration. An interconnect structure according to the present disclosure includes a conductive feature embedded in a dielectric layer, a capping barrier layer disposed over the conductive feature and the dielectric layer, and an adhesion layer sandwiched between the capping barrier layer and the dielectric layer. The adhesion layer includes a degree of crystallinity between about 40% and about 70%.

公开(公告)号：US20220359411A1

公开(公告)日：2022-11-10

申请号：US17869012

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Chen HO ,  Chien Lin ,  Cheng-Yeh Yu ,  Hsin-Hsing Chen ,  Ju Ru Hsieh

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/522

Abstract: The present disclosure provides a structure and a method to reduce electro-migration. An interconnect structure according to the present disclosure includes a conductive feature embedded in a dielectric layer, a capping barrier layer disposed over the conductive feature and the dielectric layer, and an adhesion layer sandwiched between the capping barrier layer and the dielectric layer. The adhesion layer includes a degree of crystallinity between about 40% and about 70%.