公开(公告)号：US20250072040A1

公开(公告)日：2025-02-27

申请号：US18941205

申请日：2024-11-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi Chen Ho ,  Yiting Chang ,  Lun-Kuang Tan ,  Chien Lin

IPC: H01L29/78 ,  H01L27/092 ,  H01L29/66

Abstract: In an embodiment, a method includes forming a plurality of semiconductor fins over a substrate, the plurality of semiconductor fins comprising a first fin, a second fin, a third fin, and a fourth fin; forming a first dielectric layer over the plurality of semiconductor fins, the first dielectric layer filling an entirety of a first trench between the first fin and the second fin; forming a second dielectric layer over the first dielectric layer, the second dielectric layer filling an entirety of a second trench between the second fin and the third fin, the forming the second dielectric layer comprising: forming an oxynitride layer; and forming an oxide layer; and forming a third dielectric layer over the second dielectric layer, the third dielectric layer filling an entirety of a third trench between the third fin and the fourth fin.

公开(公告)号：US20230377991A1

公开(公告)日：2023-11-23

申请号：US18366763

申请日：2023-08-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien Lin ,  Kun-Yu Lee ,  Shahaji B. More ,  Cheng-Han Lee ,  Shih-Chieh Chang

IPC: H01L21/8238 ,  H01L21/3065 ,  H01L21/308 ,  H01L27/092 ,  H01L29/04 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823821 ,  H01L21/3065 ,  H01L21/3086 ,  H01L21/823828 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A method for forming a semiconductor device includes patterning a substrate to form a strip including a first semiconductor material, forming an isolation region along a sidewall of the strip, an upper portion of the strip extending above the isolation region, forming a dummy structure along sidewalls and a top surface of the upper portion of the strip, performing a first etching process on an exposed portion of the upper portion of the strip to form a first recess, the exposed portion of the strip being exposed by the dummy structure, after performing the first etching process, reshaping the first recess to have a V-shaped bottom surface using a second etching process, wherein the second etching process is selective to first crystalline planes having a first orientation relative to second crystalline planes having a second orientation, and epitaxially growing a source/drain region in the reshaped first recess.

公开(公告)号：US12211752B2

公开(公告)日：2025-01-28

申请号：US17660436

申请日：2022-04-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien Lin ,  Kun-Yu Lee ,  Shahaji B. More ,  Cheng-Han Lee ,  Shih-Chieh Chang

IPC: H01L21/8238 ,  H01L21/3065 ,  H01L21/308 ,  H01L27/092 ,  H01L29/04 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

Abstract: A method for forming a semiconductor device includes patterning a substrate to form a strip including a first semiconductor material, forming an isolation region along a sidewall of the strip, an upper portion of the strip extending above the isolation region, forming a dummy structure along sidewalls and a top surface of the upper portion of the strip, performing a first etching process on an exposed portion of the upper portion of the strip to form a first recess, the exposed portion of the strip being exposed by the dummy structure, after performing the first etching process, reshaping the first recess to have a V-shaped bottom surface using a second etching process, wherein the second etching process is selective to first crystalline planes having a first orientation relative to second crystalline planes having a second orientation, and epitaxially growing a source/drain region in the reshaped first recess.

公开(公告)号：US20220246480A1

公开(公告)日：2022-08-04

申请号：US17660436

申请日：2022-04-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien Lin ,  Kun-Yu Lee ,  Shahaji B. More ,  Cheng-Han Lee ,  Shih-Chieh Chang

IPC: H01L21/8238 ,  H01L21/3065 ,  H01L21/308 ,  H01L27/092 ,  H01L29/04 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

Abstract: A method for forming a semiconductor device includes patterning a substrate to form a strip including a first semiconductor material, forming an isolation region along a sidewall of the strip, an upper portion of the strip extending above the isolation region, forming a dummy structure along sidewalls and a top surface of the upper portion of the strip, performing a first etching process on an exposed portion of the upper portion of the strip to form a first recess, the exposed portion of the strip being exposed by the dummy structure, after performing the first etching process, reshaping the first recess to have a V-shaped bottom surface using a second etching process, wherein the second etching process is selective to first crystalline planes having a first orientation relative to second crystalline planes having a second orientation, and epitaxially growing a source/drain region in the reshaped first recess.

公开(公告)号：US20240387292A1

公开(公告)日：2024-11-21

申请号：US18786483

申请日：2024-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien Lin ,  Kun-Yu Lee ,  Shahaji B. More ,  Cheng-Han Lee ,  Shih-Chieh Chang

IPC: H01L21/8238 ,  H01L21/3065 ,  H01L21/308 ,  H01L27/092 ,  H01L29/04 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

Abstract: A method for forming a semiconductor device includes patterning a substrate to form a strip including a first semiconductor material, forming an isolation region along a sidewall of the strip, an upper portion of the strip extending above the isolation region, forming a dummy structure along sidewalls and a top surface of the upper portion of the strip, performing a first etching process on an exposed portion of the upper portion of the strip to form a first recess, the exposed portion of the strip being exposed by the dummy structure, after performing the first etching process, reshaping the first recess to have a V-shaped bottom surface using a second etching process, wherein the second etching process is selective to first crystalline planes having a first orientation relative to second crystalline planes having a second orientation, and epitaxially growing a source/drain region in the reshaped first recess.

公开(公告)号：US11855092B2

公开(公告)日：2023-12-26

申请号：US17232309

申请日：2021-04-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi Chen Ho ,  Yiting Chang ,  Lun-Kuang Tan ,  Chien Lin

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234

CPC classification number: H01L27/0924 ,  H01L21/823418 ,  H01L21/823431 ,  H01L29/6681 ,  H01L29/7851

Abstract: In an embodiment, a method includes forming a plurality of semiconductor fins over a substrate, the plurality of semiconductor fins comprising a first fin, a second fin, a third fin, and a fourth fin; forming a first dielectric layer over the plurality of semiconductor fins, the first dielectric layer filling an entirety of a first trench between the first fin and the second fin; forming a second dielectric layer over the first dielectric layer, the second dielectric layer filling an entirety of a second trench between the second fin and the third fin, the forming the second dielectric layer comprising: forming an oxynitride layer; and forming an oxide layer; and forming a third dielectric layer over the second dielectric layer, the third dielectric layer filling an entirety of a third trench between the third fin and the fourth fin.

公开(公告)号：US20210375776A1

公开(公告)日：2021-12-02

申请号：US17017356

申请日：2020-09-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Chen Ho ,  Chien Lin ,  Cheng-Yeh Yu ,  Hsin-Hsing Chen ,  Ju Ru Hsieh

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/522

Abstract: The present disclosure provides a structure and a method to reduce electro-migration. An interconnect structure according to the present disclosure includes a conductive feature embedded in a dielectric layer, a capping barrier layer disposed over the conductive feature and the dielectric layer, and an adhesion layer sandwiched between the capping barrier layer and the dielectric layer. The adhesion layer includes a degree of crystallinity between about 40% and about 70%.

公开(公告)号：US20240332190A1

公开(公告)日：2024-10-03

申请号：US18740705

申请日：2024-06-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Chen Ho ,  Chien Lin ,  Cheng-Yeh Yu ,  Hsin-Hsing Chen ,  Ju Ru Hsieh

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/53238 ,  H01L21/76834 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76871 ,  H01L23/5226

Abstract: The present disclosure provides a structure and a method to reduce electro-migration. An interconnect structure according to the present disclosure includes a conductive feature embedded in a dielectric layer, a capping barrier layer disposed over the conductive feature and the dielectric layer, and an adhesion layer sandwiched between the capping barrier layer and the dielectric layer. The adhesion layer includes a degree of crystallinity between about 40% and about 70%.

公开(公告)号：US20220359411A1

公开(公告)日：2022-11-10

申请号：US17869012

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Chen HO ,  Chien Lin ,  Cheng-Yeh Yu ,  Hsin-Hsing Chen ,  Ju Ru Hsieh

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/522

Abstract: The present disclosure provides a structure and a method to reduce electro-migration. An interconnect structure according to the present disclosure includes a conductive feature embedded in a dielectric layer, a capping barrier layer disposed over the conductive feature and the dielectric layer, and an adhesion layer sandwiched between the capping barrier layer and the dielectric layer. The adhesion layer includes a degree of crystallinity between about 40% and about 70%.

公开(公告)号：US11367784B2

公开(公告)日：2022-06-21

申请号：US16902170

申请日：2020-06-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shahaji B. More ,  Chien Lin ,  Cheng-Han Lee ,  Shih-Chieh Chang ,  Shu Kuan

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/306 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/161 ,  H01L29/10

Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. An inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers. A source/drain epitaxial layer is formed in the source/drain space to cover the inner spacer. At least one of the first semiconductor layers has a composition which changes along a stacked direction of the first semiconductor layers and second semiconductor layers.