公开(公告)号：US20220246609A1

公开(公告)日：2022-08-04

申请号：US17727620

申请日：2022-04-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Chen HO ,  Chien LIN ,  Tzu-Wei LIN ,  Ju Ru HSIEH ,  Ching-Lun LAI ,  Ming-Kai LO

IPC: H01L27/088 ,  H01L27/108 ,  H01L27/092

Abstract: An integrated circuit die includes a FinFET transistor. The FinFET transistor includes an anti-punch through region below a channel region. Undesirable dopants are removed from the anti-punch through region during formation of the source and drain regions. When source and drain recesses are formed, a layer of dielectric material is deposited in the recesses. An annealing process is then performed. Undesirable dopants diffuse from the anti-punch through region into the layer of dielectric material during the annealing process. The layer of dielectric material is then removed. The source and drain regions are then formed by depositing semiconductor material in the recesses.

公开(公告)号：US20240297038A1

公开(公告)日：2024-09-05

申请号：US18663038

申请日：2024-05-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Chen HO ,  You-Hua CHOU ,  Yen-Hao LIAO ,  Che-Lun CHANG ,  Zhen-Cheng WU

IPC: H01L21/02 ,  H01L21/311 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L21/02203 ,  H01L21/0228 ,  H01L21/31138 ,  H01L21/7682 ,  H01L23/5329 ,  H01L23/53295 ,  H01L21/02118 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/02299 ,  H01L21/76807 ,  H01L21/76835 ,  H01L21/76843 ,  H01L21/76877

Abstract: The present disclosure provides a method. In some embodiments, the method includes forming a first porogen over a dielectric film; depositing a first dielectric monolayer over the first porogen and in contact with the dielectric film; removing the first porogen. In some embodiments, the method includes forming a first porogen over a substrate; forming a first dielectric film over the first porogen; after forming the first dielectric film, performing an UV treatment on the first porogen.

公开(公告)号：US20240371867A1

公开(公告)日：2024-11-07

申请号：US18773361

申请日：2024-07-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Chen HO ,  Chien LIN ,  Tzu-Wei LIN ,  Ju Ru HSIEH ,  Ching-Lun LAI ,  Ming-Kai LO

IPC: H01L27/088 ,  H01L27/092 ,  H10B12/00

Abstract: An integrated circuit die includes a FinFET transistor. The FinFET transistor includes an anti-punch through region below a channel region. Undesirable dopants are removed from the anti-punch through region during formation of the source and drain regions. When source and drain recesses are formed, a layer of dielectric material is deposited in the recesses. An annealing process is then performed. Undesirable dopants diffuse from the anti-punch through region into the layer of dielectric material during the annealing process. The layer of dielectric material is then removed. The source and drain regions are then formed by depositing semiconductor material in the recesses.

公开(公告)号：US20200058495A1

公开(公告)日：2020-02-20

申请号：US16103744

申请日：2018-08-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Chen HO ,  You-Hua CHOU ,  Yen-Hao LIAO ,  Che-Lun CHANG ,  Zhen-Cheng WU

IPC: H01L21/02 ,  H01L21/768 ,  H01L21/311

Abstract: A method for manufacturing a dielectric layer includes forming a first dielectric film over a substrate. A first porogen is deposited over the first dielectric film. A second dielectric film is formed on and in contact with the first dielectric film and the first porogen. The first porogen is removed.

公开(公告)号：US20220359411A1

公开(公告)日：2022-11-10

申请号：US17869012

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Chen HO ,  Chien Lin ,  Cheng-Yeh Yu ,  Hsin-Hsing Chen ,  Ju Ru Hsieh

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/522

Abstract: The present disclosure provides a structure and a method to reduce electro-migration. An interconnect structure according to the present disclosure includes a conductive feature embedded in a dielectric layer, a capping barrier layer disposed over the conductive feature and the dielectric layer, and an adhesion layer sandwiched between the capping barrier layer and the dielectric layer. The adhesion layer includes a degree of crystallinity between about 40% and about 70%.

公开(公告)号：US20210272951A1

公开(公告)日：2021-09-02

申请号：US16803965

申请日：2020-02-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Chen HO ,  Hung Chih HU ,  Hung Cheng YU ,  Ju Ru HSIEH

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device including fin field-effect transistors, includes a first gate structure extending in a first direction, a second gate structure extending the first direction and aligned with the first gate structure in the first direction, a third gate structure extending in the first direction and arranged in parallel with the first gate structure in a second direction crossing the first direction, a fourth gate structure extending the first direction, aligned with the third gate structure and arranged in parallel with the second gate structure, an interlayer dielectric layer disposed between the first to fourth gate electrodes, and a separation wall made of different material than the interlayer dielectric layer and disposed between the first and third gate structures and the second and fourth gate structures.

公开(公告)号：US20210202241A1

公开(公告)日：2021-07-01

申请号：US17199066

申请日：2021-03-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Chen HO ,  You-Hua CHOU ,  Yen-Hao LIAO ,  Che-Lun CHANG ,  Zhen-Cheng WU

IPC: H01L21/02 ,  H01L21/768 ,  H01L21/311

Abstract: A structure includes a first dielectric film and a second dielectric film. The second dielectric film is formed on and in contact with the first dielectric film, in which a first pore is formed between the first dielectric film and the second dielectric film, and a thickness of the first dielectric film is smaller than a diameter of the first pore.

公开(公告)号：US20210193653A1

公开(公告)日：2021-06-24

申请号：US16721640

申请日：2019-12-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Chen HO ,  Chien LIN ,  Tzu-Wei LIN ,  Ju Ru HSIEH ,  Ching-Lun LAI ,  Ming-Kai LO

IPC: H01L27/088 ,  H01L27/092 ,  H01L27/108

Abstract: An integrated circuit die includes a FinFET transistor. The FinFET transistor includes an anti-punch through region below a channel region. Undesirable dopants are removed from the anti-punch through region during formation of the source and drain regions. When source and drain recesses are formed, a layer of dielectric material is deposited in the recesses. An annealing process is then performed. Undesirable dopants diffuse from the anti-punch through region into the layer of dielectric material during the annealing process. The layer of dielectric material is then removed. The source and drain regions are then formed by depositing semiconductor material in the recesses.

公开(公告)号：US20200235199A1

公开(公告)日：2020-07-23

申请号：US16255567

申请日：2019-01-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Chen HO ,  Chien LIN ,  You-Hua CHOU ,  Hsing-Yuan HUANG ,  Cheng-Yu HUNG

IPC: H01L49/02 ,  H01L21/02 ,  H01L21/311 ,  H01L21/321

Abstract: A semiconductor device includes a semiconductor substrate, a capacitor, and an interconnection layer. The capacitor is over the semiconductor substrate and includes a bottom electrode, a top electrode, and an insulator layer. The top electrode has a top surface and a bottom surface rougher than the top surface of the top electrode. The insulator layer is between the bottom electrode and the top electrode. The interconnection layer is over the semiconductor substrate and is electrically connected to the capacitor.