公开(公告)号：US20220246609A1

公开(公告)日：2022-08-04

申请号：US17727620

申请日：2022-04-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Chen HO ,  Chien LIN ,  Tzu-Wei LIN ,  Ju Ru HSIEH ,  Ching-Lun LAI ,  Ming-Kai LO

IPC: H01L27/088 ,  H01L27/108 ,  H01L27/092

Abstract: An integrated circuit die includes a FinFET transistor. The FinFET transistor includes an anti-punch through region below a channel region. Undesirable dopants are removed from the anti-punch through region during formation of the source and drain regions. When source and drain recesses are formed, a layer of dielectric material is deposited in the recesses. An annealing process is then performed. Undesirable dopants diffuse from the anti-punch through region into the layer of dielectric material during the annealing process. The layer of dielectric material is then removed. The source and drain regions are then formed by depositing semiconductor material in the recesses.

公开(公告)号：US20240371867A1

公开(公告)日：2024-11-07

申请号：US18773361

申请日：2024-07-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Chen HO ,  Chien LIN ,  Tzu-Wei LIN ,  Ju Ru HSIEH ,  Ching-Lun LAI ,  Ming-Kai LO

IPC: H01L27/088 ,  H01L27/092 ,  H10B12/00

Abstract: An integrated circuit die includes a FinFET transistor. The FinFET transistor includes an anti-punch through region below a channel region. Undesirable dopants are removed from the anti-punch through region during formation of the source and drain regions. When source and drain recesses are formed, a layer of dielectric material is deposited in the recesses. An annealing process is then performed. Undesirable dopants diffuse from the anti-punch through region into the layer of dielectric material during the annealing process. The layer of dielectric material is then removed. The source and drain regions are then formed by depositing semiconductor material in the recesses.

公开(公告)号：US20160064486A1

公开(公告)日：2016-03-03

申请号：US14927144

申请日：2015-10-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shin-Yeh HUANG ,  Kai-Hsiang CHANG ,  Chih-Chen JIANG ,  Yi-Wei PENG ,  Kuan-Yu LIN ,  Ming-Shan TSAI ,  Ching-Lun LAI

IPC: H01L29/10 ,  H01L21/306 ,  H01L21/225 ,  H01L29/66

CPC classification number: H01L29/7845 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/2253 ,  H01L21/30604 ,  H01L23/535 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/36 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

Abstract: Methods for forming a semiconductor device structure are provided. The method includes providing a substrate and forming an isolation structure in the substrate. The method also includes forming a gate stack structure on the substrate and etching a portion of the substrate to form a recess in the substrate, and the recess is adjacent to the gate stack structure. The method includes forming a stressor layer in the recess, and a portion of the stressor layer is grown along the (311) and (111) crystal orientations.

Abstract translation: 提供了形成半导体器件结构的方法。 该方法包括提供衬底并在衬底中形成隔离结构。 该方法还包括在衬底上形成栅极叠层结构，并蚀刻衬底的一部分以在衬底中形成凹陷，并且凹槽与栅堆叠结构相邻。 该方法包括在凹部中形成应力层，并且应力层的一部分沿（311）和（111）晶体取向生长。

公开(公告)号：US20150187940A1

公开(公告)日：2015-07-02

申请号：US14142396

申请日：2013-12-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin-Yeh HUANG ,  Kai-Hsiang CHANG ,  Chih-Chen JIANG ,  Yi-Wei PENG ,  Kuan-Yu LIN ,  Ming-Shan TSAI ,  Ching-Lun LAI

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/7845 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/2253 ,  H01L21/30604 ,  H01L23/535 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/36 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

Abstract: Embodiments for forming a semiconductor device structure are provided. The semiconductor device structure includes a substrate and a gate stack structure formed on the substrate. The semiconductor device structure also includes gate spacers formed on sidewalls of the gate stack structure. The semiconductor device structure further includes an isolation structure formed in the substrate and a source/drain stressor structure formed adjacent to the isolation structure. The source/drain stressor structure includes a capping layer which is formed along the (311) and (111) crystal orientations.

Abstract translation: 提供了用于形成半导体器件结构的实施例。 半导体器件结构包括形成在衬底上的衬底和栅叠层结构。 半导体器件结构还包括形成在栅极堆叠结构的侧壁上的栅极间隔物。 半导体器件结构还包括形成在衬底中的隔离结构和邻近隔离结构形成的源极/漏极应力结构。 源极/漏极应力器结构包括沿（311）和（111）晶体取向形成的覆盖层。

公开(公告)号：US20210193653A1

公开(公告)日：2021-06-24

申请号：US16721640

申请日：2019-12-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Chen HO ,  Chien LIN ,  Tzu-Wei LIN ,  Ju Ru HSIEH ,  Ching-Lun LAI ,  Ming-Kai LO

IPC: H01L27/088 ,  H01L27/092 ,  H01L27/108

Abstract: An integrated circuit die includes a FinFET transistor. The FinFET transistor includes an anti-punch through region below a channel region. Undesirable dopants are removed from the anti-punch through region during formation of the source and drain regions. When source and drain recesses are formed, a layer of dielectric material is deposited in the recesses. An annealing process is then performed. Undesirable dopants diffuse from the anti-punch through region into the layer of dielectric material during the annealing process. The layer of dielectric material is then removed. The source and drain regions are then formed by depositing semiconductor material in the recesses.

公开(公告)号：US20170358663A1

公开(公告)日：2017-12-14

申请号：US15180973

申请日：2016-06-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chia-Ying LI ,  Ming-Shiou KUO ,  Wei-Ching WU ,  Zong-Han LI ,  Ching-Lun LAI

IPC: H01L29/66 ,  H01L21/8238 ,  H01L21/02

CPC classification number: H01L29/66795 ,  H01L21/02271 ,  H01L21/02348 ,  H01L21/02694 ,  H01L21/823821 ,  H01L29/6681

Abstract: A method for manufacturing a semiconductor device is provided, including forming a fin field effect transistor (FinFET) structure on a semiconductor substrate. The FinFET structure includes at least one fin, and a gate electrode structure and source/drain regions on the at least one fin. A dielectric film is formed over the at least on fin. The dielectric film is irradiated with ultra violet (UV) radiation from a single UV source.

公开(公告)号：US20170040451A1

公开(公告)日：2017-02-09

申请号：US15332800

申请日：2016-10-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shin-Yeh HUANG ,  Kai-Hsiang CHANG ,  Chih-Chen JIANG ,  Yi-Wei PENG ,  Kuan-Yu LIN ,  Ming-Shan TSAI ,  Ching-Lun LAI

IPC: H01L29/78 ,  H01L29/06 ,  H01L23/535 ,  H01L29/04 ,  H01L29/36

CPC classification number: H01L29/7845 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/2253 ,  H01L21/30604 ,  H01L23/535 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/36 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

Abstract: The semiconductor device structures are provided. The semiconductor device structure includes a gate stack structure formed on a substrate and an isolation structure formed in the substrate. The semiconductor device structure further includes a source/drain stressor structure formed between the gate stack structure and the isolation structure and a metal silicide layer formed on the source/drain stressor structure. A portion of the metal silicide layer is below a top surface of the isolation structure.

Abstract translation: 提供半导体器件结构。 半导体器件结构包括形成在衬底上的栅堆叠结构和形成在衬底中的隔离结构。 半导体器件结构还包括形成在栅极堆叠结构和隔离结构之间的源极/漏极应力结构以及形成在源极/漏极应力结构上的金属硅化物层。 金属硅化物层的一部分在隔离结构的顶表面下方。