公开(公告)号：US20240371867A1

公开(公告)日：2024-11-07

申请号：US18773361

申请日：2024-07-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Chen HO ,  Chien LIN ,  Tzu-Wei LIN ,  Ju Ru HSIEH ,  Ching-Lun LAI ,  Ming-Kai LO

IPC: H01L27/088 ,  H01L27/092 ,  H10B12/00

Abstract: An integrated circuit die includes a FinFET transistor. The FinFET transistor includes an anti-punch through region below a channel region. Undesirable dopants are removed from the anti-punch through region during formation of the source and drain regions. When source and drain recesses are formed, a layer of dielectric material is deposited in the recesses. An annealing process is then performed. Undesirable dopants diffuse from the anti-punch through region into the layer of dielectric material during the annealing process. The layer of dielectric material is then removed. The source and drain regions are then formed by depositing semiconductor material in the recesses.

公开(公告)号：US20220246609A1

公开(公告)日：2022-08-04

申请号：US17727620

申请日：2022-04-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Chen HO ,  Chien LIN ,  Tzu-Wei LIN ,  Ju Ru HSIEH ,  Ching-Lun LAI ,  Ming-Kai LO

IPC: H01L27/088 ,  H01L27/108 ,  H01L27/092

Abstract: An integrated circuit die includes a FinFET transistor. The FinFET transistor includes an anti-punch through region below a channel region. Undesirable dopants are removed from the anti-punch through region during formation of the source and drain regions. When source and drain recesses are formed, a layer of dielectric material is deposited in the recesses. An annealing process is then performed. Undesirable dopants diffuse from the anti-punch through region into the layer of dielectric material during the annealing process. The layer of dielectric material is then removed. The source and drain regions are then formed by depositing semiconductor material in the recesses.

公开(公告)号：US20210391450A1

公开(公告)日：2021-12-16

申请号：US16902170

申请日：2020-06-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shahaji B. MORE ,  Chien LIN ,  Cheng-Han LEE ,  Shih-Chieh CHANG ,  Shu KUAN

IPC: H01L29/66 ,  H01L21/306 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/10 ,  H01L29/78 ,  H01L29/161

Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. An inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers. A source/drain epitaxial layer is formed in the source/drain space to cover the inner spacer. At least one of the first semiconductor layers has a composition which changes along a stacked direction of the first semiconductor layers and second semiconductor layers.

公开(公告)号：US20210273047A1

公开(公告)日：2021-09-02

申请号：US16934887

申请日：2020-07-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shu KUAN ,  Shahaji B. MORE ,  Chien LIN ,  Cheng-Han LEE ,  Shih-Chieh CHANG

IPC: H01L29/06 ,  H01L29/423

Abstract: In a method of manufacturing a semiconductor device, a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked is formed, a sacrificial gate structure is formed over the fin structure, a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space, the first semiconductor layers are laterally etched through the source/drain space, and a source/drain epitaxial layer is formed in the source/drain space. An inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers and at least one of the spacer has width changes along vertical direction of device. At least one of the first semiconductor layers has a composition different from another of the first semiconductor layers.

公开(公告)号：US20210193653A1

公开(公告)日：2021-06-24

申请号：US16721640

申请日：2019-12-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Chen HO ,  Chien LIN ,  Tzu-Wei LIN ,  Ju Ru HSIEH ,  Ching-Lun LAI ,  Ming-Kai LO

IPC: H01L27/088 ,  H01L27/092 ,  H01L27/108

Abstract: An integrated circuit die includes a FinFET transistor. The FinFET transistor includes an anti-punch through region below a channel region. Undesirable dopants are removed from the anti-punch through region during formation of the source and drain regions. When source and drain recesses are formed, a layer of dielectric material is deposited in the recesses. An annealing process is then performed. Undesirable dopants diffuse from the anti-punch through region into the layer of dielectric material during the annealing process. The layer of dielectric material is then removed. The source and drain regions are then formed by depositing semiconductor material in the recesses.

公开(公告)号：US20200235199A1

公开(公告)日：2020-07-23

申请号：US16255567

申请日：2019-01-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Chen HO ,  Chien LIN ,  You-Hua CHOU ,  Hsing-Yuan HUANG ,  Cheng-Yu HUNG

IPC: H01L49/02 ,  H01L21/02 ,  H01L21/311 ,  H01L21/321

Abstract: A semiconductor device includes a semiconductor substrate, a capacitor, and an interconnection layer. The capacitor is over the semiconductor substrate and includes a bottom electrode, a top electrode, and an insulator layer. The top electrode has a top surface and a bottom surface rougher than the top surface of the top electrode. The insulator layer is between the bottom electrode and the top electrode. The interconnection layer is over the semiconductor substrate and is electrically connected to the capacitor.