公开(公告)号：US12068317B2

公开(公告)日：2024-08-20

申请号：US17727620

申请日：2022-04-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Chen Ho ,  Chien Lin ,  Tzu-Wei Lin ,  Ju Ru Hsieh ,  Ching-Lun Lai ,  Ming-Kai Lo

IPC: H01L27/08 ,  H01L27/088 ,  H01L27/092 ,  H10B12/00

CPC classification number: H01L27/0886 ,  H01L27/0924 ,  H10B12/36

Abstract: An integrated circuit die includes a FinFET transistor. The FinFET transistor includes an anti-punch through region below a channel region. Undesirable dopants are removed from the anti-punch through region during formation of the source and drain regions. When source and drain recesses are formed, a layer of dielectric material is deposited in the recesses. An annealing process is then performed. Undesirable dopants diffuse from the anti-punch through region into the layer of dielectric material during the annealing process. The layer of dielectric material is then removed. The source and drain regions are then formed by depositing semiconductor material in the recesses.

公开(公告)号：US11315921B2

公开(公告)日：2022-04-26

申请号：US16721640

申请日：2019-12-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Chen Ho ,  Chien Lin ,  Tzu-Wei Lin ,  Ju Ru Hsieh ,  Ching-Lun Lai ,  Ming-Kai Lo

IPC: H01L27/08 ,  H01L27/088 ,  H01L27/108 ,  H01L27/092

Abstract: An integrated circuit die includes a FinFET transistor. The FinFET transistor includes an anti-punch through region below a channel region. Undesirable dopants are removed from the anti-punch through region during formation of the source and drain regions. When source and drain recesses are formed, a layer of dielectric material is deposited in the recesses. An annealing process is then performed. Undesirable dopants diffuse from the anti-punch through region into the layer of dielectric material during the annealing process. The layer of dielectric material is then removed. The source and drain regions are then formed by depositing semiconductor material in the recesses.