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    FinFET and gate-all-around FET with selective high-k oxide deposition
    1.
    发明授权
    FinFET and gate-all-around FET with selective high-k oxide deposition 有权

    公开(公告)号：US11177361B2

    公开(公告)日：2021-11-16

    申请号：US16889245

    申请日：2020-06-01

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Tsung-Han Tsai ,  Jen-Hsiang Lu ,  Shih-Hsun Chang

    IPC: H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L29/40 ,  H01L21/02 ,  H01L29/78

    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a fin structure formed over a semiconductor substrate and a gate structure formed across the fin structure. The semiconductor device structure also includes an isolation feature over a semiconductor substrate and below a portion of the gate structure and two spacer elements respectively formed over a first sidewall and a second sidewall of the gate structure. In addition, the first sidewall is opposite to the second sidewall and the two spacer elements have hydrophobic surfaces respectively facing the first sidewall and the second sidewall, and the gate structure includes a gate dielectric layer and a gate electrode layer separating the gate dielectric layer from the hydrophobic surfaces of the two spacer elements.

    Device having work function metal stack and method of forming the same
    6.
    发明授权
    Device having work function metal stack and method of forming the same 有权

    公开(公告)号：US11201059B2

    公开(公告)日：2021-12-14

    申请号：US16701009

    申请日：2019-12-02

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Yen-Yu Chen ,  Yu-Chi Lu ,  Chih-Pin Tsao ,  Shih-Hsun Chang

    IPC: H01L21/28 ,  H01L29/49

    Abstract: A method includes removing a dummy gate to form a gate trench. A gate dielectric layer is deposited over a bottom and sidewalls of the gate trench. A first work function metal layer is deposited over the gate dielectric layer. A dummy layer is deposited over the first work function metal layer. An impurity is introduced into the dummy layer and the first work function metal layer after the dummy layer is deposited. The dummy layer is removed after the impurity is introduced into the dummy layer and the first work function metal layer. The gate trench is filled with a conductive material after the dummy layer is removed.

    Metal Gates and Manufacturing Methods Thereof
    8.
    发明申请
    Metal Gates and Manufacturing Methods Thereof 审中-公开

    公开(公告)号：US20200266282A1

    公开(公告)日：2020-08-20

    申请号：US16865640

    申请日：2020-05-04

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Jen-Hsiang Lu ,  Tsung-Han Tsai ,  Shih-Hsun Chang

    IPC: H01L29/51 ,  H01L29/66 ,  H01L21/02 ,  H01L21/3213 ,  H01L29/45

    Abstract: A semiconductor structure includes a high-k metal gate structure (HKMG) disposed over a channel region of a semiconductor layer formed over a substrate, where the HKMG includes an interfacial layer disposed over the semiconductor layer, a high-k dielectric layer disposed over the interfacial layer, and a gate electrode disposed over the high-k dielectric layer, where a length of the high-k dielectric layer is greater than a length of the gate electrode and where outer edges of the interfacial layer, the high-k dielectric layer, and the gate electrode form a step profile. The semiconductor structure further includes gate spacers having sidewall portions contacting sidewalls of the gate electrode and bottom portions contacting top portions of the high-k dielectric layer and the interfacial layer, and source/drain features disposed in the semiconductor layer adjacent to the HKMG.

    Semiconductor device and manufacturing method thereof
    10.
    发明授权
    Semiconductor device and manufacturing method thereof 有权

    公开(公告)号：US10276574B2

    公开(公告)日：2019-04-30

    申请号：US15211871

    申请日：2016-07-15

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Chia-Chun Liao ,  Chun-Sheng Liang ,  Shu-Hui Wang ,  Shih-Hsun Chang ,  Yi-Jen Chen

    IPC: H01L27/092 ,  H01L29/51 ,  H01L29/66 ,  H01L29/49 ,  H01L21/8238

    Abstract: A semiconductor device manufacturing method includes forming fins in first and second regions defined on a substrate. The fins include first fin, second fin, third fin, and fourth fin. A dielectric layer is formed over fins and a work function adjustment layer is formed over dielectric layer. A hard mask is formed covering third and fourth fins. A first conductive material layer is formed over first fin and not over second fin. A second conductive material layer is formed over first and second fins. A first metal gate electrode fill material is formed over first and second fins. The hard mask covering third and fourth fins is removed. A third conductive material layer is formed over third fin and not over fourth fin. A fourth conductive material layer is formed over third and fourth fins, and a second metal gate electrode fill material is formed over third and fourth fins.

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