公开(公告)号：US11018242B2

公开(公告)日：2021-05-25

申请号：US17011265

申请日：2020-09-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Ting Li ,  Bi-Fen Wu ,  Jen-Hsiang Lu ,  Chih-Hao Chang

IPC: H01L29/66 ,  H01L21/28 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/78 ,  H01L27/088 ,  H01L29/417

Abstract: A method includes forming a fin extending above an isolation region. A sacrificial gate stack having a first sidewall and a second sidewall opposite the first sidewall is formed over the fin. A first spacer is formed on the first sidewall of the sacrificial gate stack. A second spacer is formed on the second sidewall of the sacrificial gate stack. A patterned mask having an opening therein is formed over the sacrificial gate stack, the first spacer and the second spacer. The patterned mask extends along a top surface and a sidewall of the first spacer. The second spacer is exposed through the opening in the patterned mask. The fin is patterned using the patterned mask, the sacrificial gate stack, the first spacer and the second spacer as a combined mask to form a recess in the fin. A source/drain region is epitaxially grown in the recess.

公开(公告)号：US20200266282A1

公开(公告)日：2020-08-20

申请号：US16865640

申请日：2020-05-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jen-Hsiang Lu ,  Tsung-Han Tsai ,  Shih-Hsun Chang

IPC: H01L29/51 ,  H01L29/66 ,  H01L21/02 ,  H01L21/3213 ,  H01L29/45

Abstract: A semiconductor structure includes a high-k metal gate structure (HKMG) disposed over a channel region of a semiconductor layer formed over a substrate, where the HKMG includes an interfacial layer disposed over the semiconductor layer, a high-k dielectric layer disposed over the interfacial layer, and a gate electrode disposed over the high-k dielectric layer, where a length of the high-k dielectric layer is greater than a length of the gate electrode and where outer edges of the interfacial layer, the high-k dielectric layer, and the gate electrode form a step profile. The semiconductor structure further includes gate spacers having sidewall portions contacting sidewalls of the gate electrode and bottom portions contacting top portions of the high-k dielectric layer and the interfacial layer, and source/drain features disposed in the semiconductor layer adjacent to the HKMG.

公开(公告)号：US11177361B2

公开(公告)日：2021-11-16

申请号：US16889245

申请日：2020-06-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-Han Tsai ,  Jen-Hsiang Lu ,  Shih-Hsun Chang

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L29/40 ,  H01L21/02 ,  H01L29/78

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a fin structure formed over a semiconductor substrate and a gate structure formed across the fin structure. The semiconductor device structure also includes an isolation feature over a semiconductor substrate and below a portion of the gate structure and two spacer elements respectively formed over a first sidewall and a second sidewall of the gate structure. In addition, the first sidewall is opposite to the second sidewall and the two spacer elements have hydrophobic surfaces respectively facing the first sidewall and the second sidewall, and the gate structure includes a gate dielectric layer and a gate electrode layer separating the gate dielectric layer from the hydrophobic surfaces of the two spacer elements.

公开(公告)号：US20210288162A1

公开(公告)日：2021-09-16

申请号：US17328046

申请日：2021-05-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Ting Li ,  Bi-Fen Wu ,  Jen-Hsiang Lu ,  Chih-Hao Chang

IPC: H01L29/66 ,  H01L21/28 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/78 ,  H01L27/088 ,  H01L29/417

Abstract: A method includes forming a fin extending above an isolation region. A sacrificial gate stack having a first sidewall and a second sidewall opposite the first sidewall is formed over the fin. A first spacer is formed on the first sidewall of the sacrificial gate stack. A second spacer is formed on the second sidewall of the sacrificial gate stack. A patterned mask having an opening therein is formed over the sacrificial gate stack, the first spacer and the second spacer. The patterned mask extends along a top surface and a sidewall of the first spacer. The second spacer is exposed through the opening in the patterned mask. The fin is patterned using the patterned mask, the sacrificial gate stack, the first spacer and the second spacer as a combined mask to form a recess in the fin. A source/drain region is epitaxially grown in the recess.

公开(公告)号：US10692983B2

公开(公告)日：2020-06-23

申请号：US16368840

申请日：2019-03-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chung-Ting Li ,  Chih-Hao Chang ,  Sheng-Yu Chang ,  Jen-Hsiang Lu ,  Jyun-Yang Shen

IPC: H01L29/417 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/78 ,  H01L27/11 ,  H01L29/06 ,  H01L29/66

Abstract: In a method of manufacturing a semiconductor device, a first fin structure for an n-channel fin field effect transistor (FinFET) is formed over a substrate. An isolation insulating layer is formed over the substrate such that an upper portion of the first fin structure protrudes from the isolation insulating layer. A gate structure is formed over a part of the upper portion of the first fin structure. A first source/drain (S/D) epitaxial layer is formed over the first fin structure not covered by the gate structure. A cap epitaxial layer is formed over the first S/D epitaxial layer. The first S/D epitaxial layer includes SiP, and the cap epitaxial layer includes SiC with a carbon concentration is in a range from 0.5 atomic % to 5 atomic %.

公开(公告)号：US20190386112A1

公开(公告)日：2019-12-19

申请号：US16008920

申请日：2018-06-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jen-Hsiang Lu ,  Tsung-Han Tsai ,  Shih-Hsun Chang

IPC: H01L29/51 ,  H01L29/45 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/02

Abstract: A method of forming a semiconductor structure includes, providing a semiconductor layer, forming an interfacial layer over the semiconductor layer, depositing a high-k dielectric layer over the interfacial layer, forming a dummy gate electrode over the high-k dielectric layer, patterning the dummy gate electrode layer, the high-k dielectric layer, and the interfacial layer, resulting in a dummy gate electrode having width a width less than a width of the high-k dielectric layer, forming spacers along sidewalls of the patterned dummy gate electrode, the high-k dielectric layer, and the interfacial layer, forming source/drain features, and replacing the dummy gate electrode with a metal gate electrode to form a high-k metal gate structure.

公开(公告)号：US11848363B2

公开(公告)日：2023-12-19

申请号：US16987909

申请日：2020-08-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chung-Ting Li ,  Jen-Hsiang Lu ,  Chih-Hao Chang

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L29/49 ,  H01L29/165

CPC classification number: H01L29/41775 ,  H01L29/41791 ,  H01L29/4991 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7848 ,  H01L29/165

Abstract: A method of forming a semiconductor device includes forming a gate structure on a semiconductor substrate. A gate spacer is formed adjacent to the gate structure. The gate spacer includes a first dielectric layer and a second dielectric layer on the first dielectric layer. A plasma treatment is performed to the second dielectric layer. After performing the plasma treatment, at least a portion of the second dielectric layer is removed such that a sidewall of the first dielectric layer is exposed. A dielectric cap is formed on the gate spacer.

公开(公告)号：US11810963B2

公开(公告)日：2023-11-07

申请号：US17328046

申请日：2021-05-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Ting Li ,  Bi-Fen Wu ,  Jen-Hsiang Lu ,  Chih-Hao Chang

IPC: H01L29/66 ,  H01L21/28 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/78 ,  H01L27/088 ,  H01L29/417

CPC classification number: H01L29/66545 ,  H01L21/2815 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6681 ,  H01L29/66795 ,  H01L29/785 ,  H01L21/823468

Abstract: A method includes forming a fin extending above an isolation region. A sacrificial gate stack having a first sidewall and a second sidewall opposite the first sidewall is formed over the fin. A first spacer is formed on the first sidewall of the sacrificial gate stack. A second spacer is formed on the second sidewall of the sacrificial gate stack. A patterned mask having an opening therein is formed over the sacrificial gate stack, the first spacer and the second spacer. The patterned mask extends along a top surface and a sidewall of the first spacer. The second spacer is exposed through the opening in the patterned mask. The fin is patterned using the patterned mask, the sacrificial gate stack, the first spacer and the second spacer as a combined mask to form a recess in the fin. A source/drain region is epitaxially grown in the recess.

公开(公告)号：US10269907B2

公开(公告)日：2019-04-23

申请号：US15918394

申请日：2018-03-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chung-Ting Li ,  Chih-Hao Chang ,  Sheng-Yu Chang ,  Jen-Hsiang Lu ,  Jyun-Yang Shen

IPC: H01L21/8238 ,  H01L21/84 ,  H01L27/11 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L29/417

Abstract: In a method of manufacturing a semiconductor device, a first fin structure for an n-channel fin field effect transistor (FinFET) is formed over a substrate. An isolation insulating layer is formed over the substrate such that an upper portion of the first fin structure protrudes from the isolation insulating layer. A gate structure is formed over a part of the upper portion of the first fin structure. A first source/drain (S/D) epitaxial layer is formed over the first fin structure not covered by the gate structure. A cap epitaxial layer is formed over the first S/D epitaxial layer. The first S/D epitaxial layer includes SiP, and the cap epitaxial layer includes SiC with a carbon concentration is in a range from 0.5 atomic % to 5 atomic %.

公开(公告)号：US11776911B2

公开(公告)日：2023-10-03

申请号：US17330834

申请日：2021-05-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hung-Ming Chen ,  Yu-Chang Lin ,  Chung-Ting Li ,  Jen-Hsiang Lu ,  Hou-Ju Li ,  Chih-Pin Tsao

IPC: H01L29/66 ,  H01L29/78 ,  H01L23/535 ,  H01L21/768 ,  H01L29/417

CPC classification number: H01L23/535 ,  H01L21/76841 ,  H01L21/76897 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7848

Abstract: A method includes forming a gate structure on a substrate; forming a gate spacer on a sidewall of the gate structure; forming a carbon-containing layer on the gate spacer; diffusing carbon from the carbon-containing layer into a portion of the substrate below the gate spacer; forming a recess in the substrate on one side of the gate spacer opposite to the gate structure; and forming an epitaxy feature in the recess of the substrate.