公开(公告)号：US11569362B2

公开(公告)日：2023-01-31

申请号：US16927953

申请日：2020-07-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chia-Ming Hsu ,  Pei-Yu Chou ,  Chih-Pin Tsao ,  Kuang-Yuan Hsu ,  Jyh-Huei Chen

IPC: H01L29/66 ,  H01L29/45 ,  H01L23/485 ,  H01L21/768 ,  H01L29/417 ,  H01L23/532 ,  H01L21/3205 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/285 ,  H01L29/78 ,  H01L21/02

Abstract: A semiconductor device includes a source/drain region, a source/drain silicide layer formed on the source/drain region, and a first contact disposed over the source/drain silicide layer. The first contact includes a first metal layer, an upper surface of the first metal layer is at least covered by a silicide layer, and the silicide layer includes a same metal element as the first metal layer.

公开(公告)号：US11289417B2

公开(公告)日：2022-03-29

申请号：US16805834

申请日：2020-03-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Yu Chou ,  Jr-Hung Li ,  Liang-Yin Chen ,  Su-Hao Liu ,  Tze-Liang Lee ,  Meng-Han Chou ,  Kuo-Ju Chen ,  Huicheng Chang ,  Tsai-Jung Ho ,  Tzu-Yang Ho

IPC: H01L23/522 ,  H01L29/08 ,  H01L23/532 ,  H01L29/66 ,  H01L21/768 ,  H01L21/3105 ,  H01L29/78 ,  H01L21/02 ,  H01L23/528 ,  H01L29/06

Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a substrate, a gate structure, a dielectric structure and a contact structure. The substrate has source/drain (S/D) regions. The gate structure is on the substrate and between the S/D regions. The dielectric structure covers the gate structure. The contact structure penetrates through the dielectric structure to connect to the S/D region. A lower portion of a sidewall of the contact structure is spaced apart from the dielectric structure by an air gap therebetween, while an upper portion of the sidewall of the contact structure is in contact with the dielectric structure.

公开(公告)号：US12243940B2

公开(公告)日：2025-03-04

申请号：US18336561

申请日：2023-06-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Hsun Wang ,  Chen-Ming Lee ,  Kuo-Yi Chao ,  Mei-Yun Wang ,  Pei-Yu Chou ,  Kuo-Ju Chen

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/762 ,  H01L21/764 ,  H01L27/088 ,  H01L29/417

Abstract: A semiconductor structure includes a source/drain (S/D) feature disposed in a semiconductor layer, a metal gate stack (MG) disposed in a first interlayer dielectric (ILD) layer and adjacent to the S/D feature, a second ILD layer disposed over the MG, and an S/D contact disposed over the S/D feature. The semiconductor structure further includes an air gap disposed between a sidewall of a bottom portion of the S/D contact and the first ILD layer, where a sidewall of a top portion of the S/D contact is in direct contact with the second ILD layer.

公开(公告)号：US20230387228A1

公开(公告)日：2023-11-30

申请号：US18366469

申请日：2023-08-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Yu Chou ,  Jr-Hung Li ,  Tze-Liang Lee

IPC: H01L29/417 ,  H01L23/535 ,  H01L29/40 ,  H01L29/78 ,  H01L21/768

CPC classification number: H01L29/41791 ,  H01L23/535 ,  H01L29/401 ,  H01L29/7851 ,  H01L21/76897 ,  H01L21/76832

Abstract: A semiconductor device a method of forming the same are provided. A semiconductor device includes a gate stack over a substrate. A first dielectric layer is over the gate stack. The first dielectric layer includes a first material. A second dielectric layer is over the first dielectric layer. The second dielectric layer includes a second material different from the first material. A first conductive feature is adjacent the gate stack. A second conductive feature is over and in physical contact with a topmost surface of the first conductive feature. A bottommost surface of the second conductive feature is in physical contact with a topmost surface of the second dielectric layer.

公开(公告)号：US20230386848A1

公开(公告)日：2023-11-30

申请号：US18230712

申请日：2023-08-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Yu Chou ,  Tze-Liang Lee

IPC: H01L21/28 ,  H01L21/768 ,  H01L29/66 ,  H01L29/40

CPC classification number: H01L21/28247 ,  H01L21/76816 ,  H01L21/76802 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/401 ,  H01L21/31116

Abstract: A method includes forming a dummy gate stack on a semiconductor fin, forming gate spacers on sidewalls of the dummy gate stack, forming a first inter-layer dielectric, with the gate spacers and the dummy gate stack being in the first inter-layer dielectric, removing the dummy gate stack to form a trench between the gate spacers, forming a replacement gate stack in the trench, and depositing a dielectric capping layer. A bottom surface of the dielectric capping layer contacts a first top surface of the replacement gate stack and a second top surface of the first inter-layer dielectric. A second inter-layer dielectric is deposited over the dielectric capping layer. A source/drain contact plug is formed and extends into the second inter-layer dielectric, the dielectric capping layer, and the first inter-layer dielectric.

公开(公告)号：US11682729B2

公开(公告)日：2023-06-20

申请号：US17576725

申请日：2022-01-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Hsun Wang ,  Chen-Ming Lee ,  Kuo-Yi Chao ,  Mei-Yun Wang ,  Pei-Yu Chou ,  Kuo-Ju Chen

IPC: H01L29/78 ,  H01L21/02 ,  H01L27/088 ,  H01L29/417 ,  H01L21/762 ,  H01L21/764

CPC classification number: H01L29/7848 ,  H01L21/02532 ,  H01L21/764 ,  H01L21/76224 ,  H01L27/0886 ,  H01L29/41791

Abstract: A semiconductor structure includes a source/drain (S/D) feature disposed in a semiconductor layer, a metal gate stack (MG) disposed in a first interlayer dielectric (ILD) layer and adjacent to the S/D feature, a second ILD layer disposed over the MG, and an S/D contact disposed over the S/D feature. The semiconductor structure further includes an air gap disposed between a sidewall of a bottom portion of the S/D contact and the first ILD layer, where a sidewall of a top portion of the S/D contact is in direct contact with the second ILD layer.

公开(公告)号：US20210083114A1

公开(公告)日：2021-03-18

申请号：US16572320

申请日：2019-09-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Hsun Wang ,  Chen-Ming Lee ,  Kuo-Yi Chao ,  Mei-Yun Wang ,  Pei-Yu Chou ,  Kuo-Ju Chen

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/764 ,  H01L29/417 ,  H01L21/762 ,  H01L27/088

Abstract: A semiconductor structure includes a source/drain (S/D) feature disposed in a semiconductor layer, a metal gate stack (MG) disposed in a first interlayer dielectric (ILD) layer and adjacent to the S/D feature, a second ILD layer disposed over the MG, and an S/D contact disposed over the S/D feature. The semiconductor structure further includes an air gap disposed between a sidewall of a bottom portion of the S/D contact and the first ILD layer, where a sidewall of a top portion of the S/D contact is in direct contact with the second ILD layer.

公开(公告)号：US20240387179A1

公开(公告)日：2024-11-21

申请号：US18785509

申请日：2024-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Yu Chou ,  Tze-Liang Lee

IPC: H01L21/28 ,  H01L21/311 ,  H01L21/768 ,  H01L27/088 ,  H01L29/40 ,  H01L29/417 ,  H01L29/66

Abstract: A method includes forming a dummy gate stack on a semiconductor fin, forming gate spacers on sidewalls of the dummy gate stack, forming a first inter-layer dielectric, with the gate spacers and the dummy gate stack being in the first inter-layer dielectric, removing the dummy gate stack to form a trench between the gate spacers, forming a replacement gate stack in the trench, and depositing a dielectric capping layer. A bottom surface of the dielectric capping layer contacts a first top surface of the replacement gate stack and a second top surface of the first inter-layer dielectric. A second inter-layer dielectric is deposited over the dielectric capping layer. A source/drain contact plug is formed and extends into the second inter-layer dielectric, the dielectric capping layer, and the first inter-layer dielectric.

公开(公告)号：US20230043635A1

公开(公告)日：2023-02-09

申请号：US17654627

申请日：2022-03-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Yu Chou ,  Chia-Ming Hsu ,  Tze-Liang Lee

IPC: H01L21/768 ,  H01L23/522

Abstract: A method includes forming a gate structure over a substrate; forming a source/drain region adjacent the gate structure; forming a first interlayer dielectric (ILD) over the source/drain region; forming a contact plug extending through the first ILD that electrically contacts the source/drain region; forming a silicide layer on the contact plug; forming a second ILD extending over the first ILD and the silicide layer; etching an opening extending through the second ILD and the silicide layer to expose the contact plug, wherein the silicide layer is used as an etch stop during the etching of the opening; and forming a conductive feature in the opening that electrically contacts the contact plug.

公开(公告)号：US20220123115A1

公开(公告)日：2022-04-21

申请号：US17193626

申请日：2021-03-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Yu Chou ,  Jr-Hung Li ,  Tze-Liang Lee

IPC: H01L29/417 ,  H01L29/78 ,  H01L29/40 ,  H01L23/535

Abstract: A semiconductor device a method of forming the same are provided. A semiconductor device includes a gate stack over a substrate. A first dielectric layer is over the gate stack. The first dielectric layer includes a first material. A second dielectric layer is over the first dielectric layer. The second dielectric layer includes a second material different from the first material. A first conductive feature is adjacent the gate stack. A second conductive feature is over and in physical contact with a topmost surface of the first conductive feature. A bottommost surface of the second conductive feature is in physical contact with a topmost surface of the second dielectric layer.