公开(公告)号：US20170047323A1

公开(公告)日：2017-02-16

申请号：US15339779

申请日：2016-10-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Han-Min TSAI ,  Chi-Feng HUANG ,  Chia-Chung CHEN ,  Victor Chiang LIANG ,  Hsiao-Chun LEE ,  Shou-Chun CHOU ,  Shu-Fang FU

IPC: H01L27/082 ,  H01L27/02 ,  H01L29/08 ,  H01L29/10 ,  H01L29/06 ,  H01L29/735

CPC classification number: H01L27/082 ,  H01L23/562 ,  H01L27/0207 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/1008 ,  H01L29/41708 ,  H01L29/42304 ,  H01L29/735

Abstract: A bipolar junction transistor includes an emitter, a base contact, a collector and a shallow trench isolation. The base contact has two base fingers that form a corner to receive the emitter. The collector has two collector fingers extending along the base fingers of the base contact. The shallow trench isolation is disposed in between the emitter and the base contact and in between the base contact and the collector.

Abstract translation: 双极结型晶体管包括发射极，基极接触，集电极和浅沟槽隔离。 基座触点具有形成角部以接收发射器的两个基部指状物。 收集器具有沿基座触点的基部指状物延伸的两个收集器指状物。 浅沟槽隔离设置在发射极和基极触点之间以及基极触点和集电极之间。

公开(公告)号：US20140295640A1

公开(公告)日：2014-10-02

申请号：US14302476

申请日：2014-06-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Feng HUANG ,  Chia-Chung CHEN

IPC: H01L49/02 ,  H01L27/08

CPC classification number: H01L27/0805 ,  H01L23/5223 ,  H01L27/016 ,  H01L27/0207 ,  H01L28/40 ,  H01L28/60 ,  H01L28/86 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of forming semiconductor devices. The method includes forming a capacitor array comprising a plurality of cells in a two-dimensional grid. The step of forming includes forming a plurality of operational capacitors in a first subset of the plurality of cells along a diagonal of the array, the plurality of operational capacitors comprising a first operational capacitor formed in a cell at a first edge of the capacitor array and at a first edge of the diagonal of the capacitor array. The step of forming also includes forming a plurality of dummy patterns about the plurality of operational capacitors in the capacitor array in a second subset of the plurality of cells to achieve symmetry in the grid about the diagonal. The method also includes electrically coupling each one of the plurality of operational capacitors to another one of the plurality of operational capacitors.

Abstract translation: 形成半导体器件的方法。 该方法包括形成包括二维网格中的多个单元的电容器阵列。 形成步骤包括沿阵列的对角线在多个单元的第一子集中形成多个工作电容器，所述多个工作电容器包括形成在电容器阵列的第一边缘处的单元中的第一工作电容器，以及 在电容器阵列的对角线的第一边缘处。 形成步骤还包括在多个单元的第二子集中的电容器阵列中的多个工作电容器周围形成多个虚拟图案，以实现围绕对角线的栅格对称。 该方法还包括将多个工作电容器中的每一个电耦合到多个工作电容器中的另一个。

公开(公告)号：US20150015336A1

公开(公告)日：2015-01-15

申请号：US13939209

申请日：2013-07-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Jin YEH ,  Chewn-Pu JOU ,  Jun-De JIN ,  Hsieh-Hung HSIEH ,  Chia-Chung CHEN

IPC: H03F3/213 ,  H01L21/8238

CPC classification number: H03F3/213 ,  H01L21/8238 ,  H01L27/092 ,  H01L2924/3011 ,  H03F1/223

Abstract: A circuit includes a first CMOS device forming a gain stage of a power amplifier and a second CMOS device forming a voltage buffer stage of the power amplifier. The first CMOS device includes a first doped well formed in a substrate, a first drain region and a first source region spaced laterally from one another in the first doped well, and a first gate structure formed over a first channel region in the first doped well. The second CMOS device includes a second doped well formed in the semiconductor substrate such that the first doped well and the second is disposed adjacent to the second doped well. A second drain region and a second source region are spaced laterally from one another in the second doped well, and a second gate structure formed over a second channel region in the second doped well.

Abstract translation: 电路包括形成功率放大器的增益级的第一CMOS器件和形成功率放大器的电压缓冲级的第二CMOS器件。 第一CMOS器件包括形成在衬底中的第一掺杂阱，第一漏极区和在第一掺杂阱中彼此横向间隔开的第一源极区，以及形成在第一掺杂阱中的第一沟道区上的第一栅极结构 。 第二CMOS器件包括在半导体衬底中形成的第二掺杂阱，使得第一掺杂阱和第二掺杂阱邻近第二掺杂阱设置。 第二漏极区域和第二源极区域在第二掺杂阱中彼此横向隔开，第二栅极结构形成在第二掺杂阱中的第二沟道区域上。

公开(公告)号：US20170018511A1

公开(公告)日：2017-01-19

申请号：US14801036

申请日：2015-07-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Shuo-Chun CHOU ,  Chi-Feng HUANG ,  Chia-Chung CHEN ,  Victor Chiang LIANG

IPC: H01L23/58 ,  H01L23/522

CPC classification number: H01L23/585 ,  H01L23/5223 ,  H01L23/5225 ,  H01L23/5227

Abstract: A semiconductor device is provided. The semiconductor device includes a seal ring and a noise-absorbing circuit. The noise-absorbing circuit is electrically connected between the seal ring and a ground pad. The noise-absorbing circuit includes at least one capacitor and at least one inductor to form a first noise-absorbing path, a second noise-absorbing path and a third noise-absorbing path.

Abstract translation: 提供半导体器件。 半导体器件包括密封环和噪声吸收电路。 噪声吸收电路电连接在密封环和接地垫之间。 噪声吸收电路包括至少一个电容器和至少一个电感器，以形成第一噪声吸收路径，第二噪声吸收路径和第三噪声吸收路径。

公开(公告)号：US20160358912A1

公开(公告)日：2016-12-08

申请号：US14732670

申请日：2015-06-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chia-Chung CHEN ,  Chi-Feng HUANG ,  Victor Chiang LIANG ,  Fu-Huan TSAI ,  Hsieh-Hung HSIEH ,  Tzu-Jin YEH ,  Han-Min TSAI ,  Hong-Lin CHU

IPC: H01L27/088 ,  H01L21/265 ,  H03D7/14 ,  H01L21/266 ,  H01L29/06 ,  H01L29/10 ,  H01L21/8234 ,  H01L29/167

CPC classification number: H03D7/1441 ,  H01L21/823412 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/1033 ,  H01L29/167 ,  H01L29/66795 ,  H01L29/785 ,  H03D7/1458

Abstract: A method for manufacturing a semiconductor device including an upper-channel implant transistor is provided. The method includes forming one or more fins extending in a first direction over a substrate. The one or more fins include a first region along the first direction and second regions on both sides of the first region along the first direction. A dopant is shallowly implanted in an upper portion of the first region of the fins but not in the second regions and not in a lower portion of the first region of the fins. A gate structure extending in a second direction perpendicular to the first direction is formed overlying the first region of the fins, and source/drains are formed overlying the second regions of the fins, thereby forming an upper-channel implant transistor.

Abstract translation: 提供一种制造包括上通道注入晶体管的半导体器件的方法。 该方法包括形成在衬底上沿第一方向延伸的一个或多个翅片。 一个或多个翅片包括沿第一方向的第一区域和沿着第一方向的第一区域两侧的第二区域。 掺杂剂浅地植入翅片的第一区域的上部，而不是在翅片的第一区域的第二区域中而不是在下部。 形成在垂直于第一方向的第二方向上延伸的栅极结构，覆盖鳍片的第一区域，并且形成覆盖翅片的第二区域的源极/漏极，从而形成上沟道注入晶体管。

公开(公告)号：US20140291806A1

公开(公告)日：2014-10-02

申请号：US14302471

申请日：2014-06-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Feng HUANG ,  Chia-Chung CHEN

IPC: H01L27/08 ,  H01L27/02 ,  H01L49/02

CPC classification number: H01L27/0805 ,  H01L23/5223 ,  H01L27/016 ,  H01L27/0207 ,  H01L28/40 ,  H01L28/60 ,  H01L28/86 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor devices having capacitor arrays. A semiconductor device is formed including a capacitor array formed in a plurality of cells in a two-dimensional grid. The capacitor array includes a plurality of operational capacitors formed in a first subset of the plurality of cells along a diagonal of the capacitor array. A first operational capacitor is formed in a cell at a first edge of the capacitor array and at a first edge of the diagonal of the capacitor array. The capacitor array also includes a plurality of dummy patterns formed about the plurality of operational capacitors in the capacitor array in a second subset of the plurality of cells to achieve symmetry in the grid about the diagonal. Each one of the plurality of operational capacitors is electrically coupled to another one of the plurality of operational capacitors.

Abstract translation: 具有电容器阵列的半导体器件。 形成半导体器件，其包括形成在二维栅格中的多个单元中的电容器阵列。 电容器阵列包括沿着电容器阵列的对角线形成在多个单元的第一子集中的多个工作电容器。 在电容器阵列的第一边缘处的单元中并且在电容器阵列的对角线的第一边缘处形成第一操作电容器。 电容器阵列还包括在多个单元的第二子集中围绕电容器阵列中的多个工作电容器形成的多个虚拟图案，以实现围绕对角线的栅格对称。 多个工作电容器中的每一个电耦合到多个工作电容器中的另一个。

公开(公告)号：US20180277662A1

公开(公告)日：2018-09-27

申请号：US15468880

申请日：2017-03-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Victor Chiang LIANG ,  Chia-Chung CHEN ,  Chi-Feng HUANG ,  Shu-Fang FU

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/78 ,  H01L29/417 ,  H01L23/522

CPC classification number: H01L29/66795 ,  H01L29/0847 ,  H01L29/41775 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/785

Abstract: A method for forming a semiconductor device is provided. The method includes forming a gate structure over a fin structure. The method includes forming a hard mask layer over the gate structure. The hard mask layer has a first opening spaced apart from a first side of the gate structure by a first distance and a second opening spaced apart from a second side of the gate structure by a second distance that is different from the first distance. The method also includes removing the fin structure not covered by the hard mask layer. The method further includes forming a first source/drain feature in the fin structure and filling the first opening of the hard mask layer. The method further includes forming a second source/drain feature in the fin structure and filling the second opening of the hard mask layer.

公开(公告)号：US20160358911A1

公开(公告)日：2016-12-08

申请号：US14732661

申请日：2015-06-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chia-Chung CHEN ,  Chi-Feng HUANG ,  Victor Chiang LIANG ,  Fu-Huan TSAI ,  Hsieh-Hung HSIEH ,  Tzu-Jin YEH ,  Han-Min TSAI ,  Hong-Lin CHU

IPC: H01L27/088 ,  H01L21/265 ,  H01L29/167 ,  H01L21/266 ,  H03D7/14 ,  H01L29/10 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L21/8234 ,  H01L21/027

CPC classification number: H01L27/0886 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/1033 ,  H01L29/167 ,  H01L29/41783 ,  H01L29/42376 ,  H03D7/1441 ,  H03D7/1458

Abstract: A method for manufacturing a semiconductor device includes forming one or more fins extending in a first direction over a substrate. The one or more fins include a first region along the first direction and second regions on both sides of the first region along the first direction. A dopant is implanted in the first region of the fins but not in the second regions. A gate structure overlies the first region of the fins and source/drains are formed on the second regions of the fins.

Abstract translation: 一种制造半导体器件的方法包括形成沿衬底上沿第一方向延伸的一个或多个鳍。 一个或多个翅片包括沿第一方向的第一区域和沿着第一方向的第一区域两侧的第二区域。 掺杂剂注入散热片的第一区域，但不在第二区域中。 栅极结构覆盖翅片的第一区域，并且在鳍片的第二区域上形成源极/漏极。