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    Semiconductor memory device
    1.
    发明授权
    Semiconductor memory device 有权

    公开(公告)号：US11074969B2

    公开(公告)日：2021-07-27

    申请号：US17071505

    申请日：2020-10-15

    Applicant: TOSHIBA MEMORY CORPORATION

    Inventor： Noboru Shibata

    IPC: G11C16/10 ,  G11C11/56 ,  G11C16/34 ,  G11C16/04

    Abstract: According to one embodiment, a semiconductor memory device includes a memory cell array, a data storage circuit and a control circuit. The data storage circuit holds first data to be written into the memory cell and holds 1 bit data calculated from the first data. The control circuit writes the data of n bits into the memory cell in a first write operation and then executes a second write operation. The control circuit carries out the following control in the second write operation. It reads data stored in the memory cell in the first write operation. It restores the first data based on the data read from the memory cell and the 1 bit data held in the data storage circuit. It writes the restored first data into the memory cell.

    Semiconductor memory device and memory system
    2.
    发明授权
    Semiconductor memory device and memory system 有权

    公开(公告)号：US10916300B2

    公开(公告)日：2021-02-09

    申请号：US16896601

    申请日：2020-06-09

    Applicant: TOSHIBA MEMORY CORPORATION

    Inventor： Noboru Shibata ,  Tokumasa Hara

    IPC: G11C11/56 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/32 ,  G11C16/34 ,  G11C16/04 ,  G06F13/16

    Abstract: According to one embodiment, a semiconductor memory device includes a first memory cell capable of storing 3-bit data. When first data including a first bit is received from an external controller, the received first data is written to the first memory cell. When second data including a second bit and a third bit is received from the controller after the first data is received, the first bit is read from the first memory cell and the 3-bit data is written to the first memory cell based on the read first bit and the received second data. In the 3-bit data written to the first memory cell, lower bit data is determined by three read operations, middle bit data is determined by two read operations, and upper bit data is determined by two read operations.

    Semiconductor memory device
    3.
    发明授权
    Semiconductor memory device 有权

    公开(公告)号：US10796779B2

    公开(公告)日：2020-10-06

    申请号：US16800180

    申请日：2020-02-25

    Applicant: TOSHIBA MEMORY CORPORATION

    Inventor： Hiroshi Maejima ,  Noboru Shibata

    IPC: G11C11/34 ,  G11C16/34 ,  G11C16/26 ,  G11C16/10 ,  G11C16/24 ,  G11C16/08 ,  G11C11/56 ,  G11C16/04

    Abstract: A semiconductor memory device includes a first memory cell which is capable of being set to any one of at least eight threshold voltages, a first bit line connected to the first memory cell, a word line connected to a gate of the first memory cell, a sense amplifier connected to the first bit line, wherein the sense amplifier has at least four data latch circuits, and an extra data latch circuit connected to the sense amplifier through a data bus. A verification operation for verifying the threshold voltage of the first memory cell is performed after a programming operation is performed on the first memory cell, and the verification operation includes seven verification operations during which the four data latch circuits, but not the extra data latch circuit, are accessed.

    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE WHICH PERFORMS IMPROVED ERASE OPERATION
    4.
    发明申请
    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE WHICH PERFORMS IMPROVED ERASE OPERATION 审中-公开

    公开(公告)号：US20200273524A1

    公开(公告)日：2020-08-27

    申请号：US16871578

    申请日：2020-05-11

    Applicant: Toshiba Memory Corporation

    Inventor： Jun Nakai ,  Noboru Shibata

    IPC: G11C16/16 ,  G11C16/14 ,  G11C16/34 ,  G11C16/26

    Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control unit. The memory cell array includes a plurality of memory cells arranged in a matrix. The control unit erases data of the memory cells. The control unit interrupts the erase operation of the memory cells and holds an erase condition before the interrupt in accordance with a first command during the erase operation, and resumes the erase operation based on the held erase condition in accordance with a second command.

    Semiconductor memory device and memory system
    5.
    发明授权
    Semiconductor memory device and memory system 有权

    公开(公告)号：US10714170B2

    公开(公告)日：2020-07-14

    申请号：US16733491

    申请日：2020-01-03

    Applicant: TOSHIBA MEMORY CORPORATION

    Inventor： Noboru Shibata ,  Tokumasa Hara

    IPC: G11C11/56 ,  G11C16/10 ,  G11C16/26 ,  G11C16/08 ,  G11C16/04 ,  G11C16/32 ,  G11C16/34 ,  G06F13/16

    Abstract: According to one embodiment, a semiconductor memory device includes a first memory cell capable of storing 3-bit data. When first data including a first bit is received from an external controller, the received first data is written to the first memory cell. When second data including a second bit and a third bit is received from the controller after the first data is received, the first bit is read from the first memory cell and the 3-bit data is written to the first memory cell based on the read first bit and the received second data. In the 3-bit data written to the first memory cell, lower bit data is determined by three read operations, middle bit data is determined by two read operations, and upper bit data is determined by two read operations.

    Nonvolatile memory and writing method
    9.
    发明授权
    Nonvolatile memory and writing method 有权

    公开(公告)号：US11270765B2

    公开(公告)日：2022-03-08

    申请号：US17154513

    申请日：2021-01-21

    Applicant: Toshiba Memory Corporation

    Inventor： Tokumasa Hara ,  Noboru Shibata

    IPC: G11C11/56 ,  G11C16/04

    Abstract: According to one embodiment, three bits stored in one memory cell of a nonvolatile memory correspond to three pages. In first page writing, a threshold voltage becomes within a first or second region base on a bit value. In second page writing, if being within the first region, it becomes within the first or fourth region; and if being within the second region, it becomes within the second or third region. In the third page writing, if being within the first region, it becomes within the first or sixth region; if being within the second region, it becomes within the second or seventh region; being within the third region, it becomes within the third or eighth region; and if being within the fourth region, it becomes within the fourth or fifth region.

    Semiconductor memory device and memory system
    10.
    发明授权
    Semiconductor memory device and memory system 有权

    公开(公告)号：US11238925B2

    公开(公告)日：2022-02-01

    申请号：US17137723

    申请日：2020-12-30

    Applicant: TOSHIBA MEMORY CORPORATION

    Inventor： Noboru Shibata ,  Tokumasa Hara

    IPC: G11C11/56 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/32 ,  G11C16/34 ,  G11C16/04 ,  G06F13/16

    Abstract: A semiconductor memory device includes a first memory cell for storing data using at least three levels of threshold voltages, including a first level, a second level higher than the first level and a third level higher than the second level. A first word line is connected to the first memory cell. In writing of data to the first memory cell from a state where a threshold voltage of the first memory cell is the first level, a plurality of program operations and verify operations are performed, each program operation including applying a program voltage to the first word line, each verify operation including applying a read voltage lower than the program voltage. The program operations include a program operation for the second level and a program operation for the third level, and the verify operations include a verify operation for the second level, and do not include a verify operation for the third level.

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