公开(公告)号：US10885988B2

公开(公告)日：2021-01-05

申请号：US16519286

申请日：2019-07-23

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Takayuki Akamine ,  Masanobu Shirakawa ,  Tokumasa Hara

IPC: G11C16/26 ,  G11C16/10 ,  G11C16/08 ,  G11C7/22 ,  G11C16/32 ,  G11C29/44

Abstract: A memory system of an embodiment includes a memory device including a first set of cell transistors and a second set of cell transistors; and a controller configured to transmit to the memory device a first instruction and transmit to the memory device a second instruction after reception of a first request without receiving the first request again. The first instruction instructs parallel reads from the first and second sets of cell transistors, and the second instruction instructs a read from the first set of cell transistors.

公开(公告)号：US10255971B2

公开(公告)日：2019-04-09

申请号：US14621894

申请日：2015-02-13

Applicant: Toshiba Memory Corporation

Inventor： Tokumasa Hara ,  Noboru Shibata

IPC: G11C11/407 ,  G11C11/56 ,  G11C16/04

Abstract: According to one embodiment, three bits stored in one memory cell of a nonvolatile memory correspond to three pages. In first page writing, a threshold voltage becomes within a first or second region base on a bit value. In second page writing, if being within the first region, it becomes within the first or fourth region; and if being within the second region, it becomes within the second or third region. In the third page writing, if being within the first region, it becomes within the first or sixth region; if being within the second region, it becomes within the second or seventh region; if being within the third region, it becomes within the third or eighth region; and if being within the fourth region, it becomes within the fourth or fifth region.

公开(公告)号：US10180876B2

公开(公告)日：2019-01-15

申请号：US15058624

申请日：2016-03-02

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Tokumasa Hara

IPC: G11C29/00 ,  G06F11/10 ,  G11C29/52

Abstract: A memory controller includes: a host interface configured to receive a read command from the outside of the memory controller; and a read controller configured to perform a data read operation on a memory device according to the read command. The read controller performs a data read operation on a set of memory cells and determines a first and second values. The first value is a number of memory cells having a first threshold voltage among the set of memory cells, and the second value is a number of memory cells having a second threshold voltage among the set of memory cells. The read controller determines a first read voltage based on only the first and second values and performs a data read operation on the set of memory cells using the first read voltage.

公开(公告)号：US09966146B2

公开(公告)日：2018-05-08

申请号：US14636321

申请日：2015-03-03

Applicant: Toshiba Memory Corporation

Inventor： Daiki Watanabe ,  Hiroshi Sukegawa ,  Hiroshi Yao ,  Tokumasa Hara ,  Naomi Takeda

IPC: G11C29/00 ,  G11C16/26 ,  G11C29/52 ,  G11C11/56 ,  G06F11/10 ,  G11C8/12 ,  G11C29/04

CPC classification number: G11C16/26 ,  G06F11/1048 ,  G11C8/12 ,  G11C11/5642 ,  G11C29/52 ,  G11C2029/0411

Abstract: According to one embodiment, a controller groups a plurality of memory cells in each of the pages into a plurality of groups. The plurality of groups includes a first group and a second group. In a case of reading data from a first page, The controller performs first reading. The first reading includes reading data from the first page by using a first operation parameter for the first group. The controller performs second reading. The second reading includes reading data from the first page by using a second operation parameter for the second group. The controller merges first read data and second read data, and return the merged data as read data read from the first page. The first read data is acquired by the first reading. The second read data is acquired by the second reading.

公开(公告)号：US09928920B2

公开(公告)日：2018-03-27

申请号：US14976842

申请日：2015-12-21

Applicant: Toshiba Memory Corporation

Inventor： Yasuhiko Kurosawa ,  Tsuyoshi Atsumi ,  Masanobu Shirakawa ,  Tokumasa Hara ,  Naoya Tokiwa

IPC: G11C16/34 ,  G06F11/10 ,  G11C29/52 ,  G06F3/06 ,  G11C16/26 ,  G11C7/04 ,  G11C16/04 ,  G11C11/56

CPC classification number: G11C16/3404 ,  G06F11/1048 ,  G06F11/1068 ,  G11C7/04 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/26 ,  G11C29/52

Abstract: According to one embodiment, a temperature of a non-volatile memory or an ambient temperature of the non-volatile memory is acquired. A distribution of a threshold voltage, which is corrected according to the acquired temperature, is acquired from the non-volatile memory. Read voltages related to the reading of data are detected from the distribution. Error correction is performed for data read from the non-volatile memory, using the read voltages. The detected read voltages are separately corrected on the basis of the acquired temperature when the error correction has failed.

公开(公告)号：US10937490B2

公开(公告)日：2021-03-02

申请号：US16919860

申请日：2020-07-02

Applicant: Toshiba Memory Corporation

Inventor： Tokumasa Hara ,  Noboru Shibata

IPC: G11C11/56 ,  G11C16/04

Abstract: According to one embodiment, three bits stored in one memory cell of a nonvolatile memory correspond to three pages. In first page writing, a threshold voltage becomes within a first or second region base on a bit value. In second page writing, if being within the first region, it becomes within the first or fourth region; and if being within the second region, it becomes within the second or third region. In the third page writing, if being within the first region, it becomes within the first or sixth region; if being within the second region, it becomes within the second or seventh region; if being within the third region, it becomes within the third or eighth region; and if being within the fourth region, it becomes within the fourth or fifth region.

公开(公告)号：US10790017B2

公开(公告)日：2020-09-29

申请号：US16529322

申请日：2019-08-01

Applicant: Toshiba Memory Corporation

Inventor： Tokumasa Hara ,  Noboru Shibata

IPC: G11C11/56 ,  G11C16/04

Abstract: According to one embodiment, three bits stored in one memory cell of a nonvolatile memory correspond to three pages. In first page writing, a threshold voltage becomes within a first or second region base on a bit value. In second page writing, if being within the first region, it becomes within the first or fourth region; and if being within the second region, it becomes within the second or third region. In the third page writing, if being within the first region, it becomes within the first or sixth region; if being within the second region, it becomes within the second or seventh region; if being within the third region, it becomes within the third or eighth region; and if being within the fourth region, it becomes within the fourth or fifth region.

公开(公告)号：US10545691B2

公开(公告)日：2020-01-28

申请号：US16011920

申请日：2018-06-19

Applicant: Toshiba Memory Corporation

Inventor： Riki Suzuki ,  Toshikatsu Hida ,  Tokumasa Hara

IPC: G11C11/16 ,  G06F3/06 ,  G11C16/34 ,  G11C16/12 ,  G11C29/52 ,  G11C16/04 ,  H01L27/115 ,  H01L27/11582

Abstract: According to one embodiment, a controller executes first refreshing in a case where a first value of a first block is larger than a first threshold and less than a second threshold. The first refreshing includes reprogramming a plurality of second memory cells among a plurality of first memory cells included in the first block.

公开(公告)号：US20190355412A1

公开(公告)日：2019-11-21

申请号：US16529322

申请日：2019-08-01

Applicant: Toshiba Memory Corporation

Inventor： Tokumasa Hara ,  Noboru Shibata

IPC: G11C11/56

Abstract: According to one embodiment, three bits stored in one memory cell of a nonvolatile memory correspond to three pages. In first page writing, a threshold voltage becomes within a first or second region base on a bit value. In second page writing, if being within the first region, it becomes within the first or fourth region; and if being within the second region, it becomes within the second or third region. In the third page writing, if being within the first region, it becomes within the first or sixth region; if being within the second region, it becomes within the second or seventh region; if being within the third region, it becomes within the third or eighth region; and if being within the fourth region, it becomes within the fourth or fifth region.

公开(公告)号：US10289480B2

公开(公告)日：2019-05-14

申请号：US14847083

申请日：2015-09-08

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Naomi Takeda ,  Tokumasa Hara ,  Masanobu Shirakawa ,  Hiroshi Yao

IPC: G06F11/00 ,  G06F11/08 ,  G06F12/00 ,  G11C29/00 ,  G11C29/44 ,  G11C16/04

Abstract: A memory system includes a memory and a controller. The memory includes a first memory chip and a second memory chip. The controller controls the memory. Each of the first and second memory chips includes string units and blocks including the string units. The memory holds information indicating a partial bad block including a bad string unit, and indicating which one of string units is the bad string unit in the partial bad block.