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公开(公告)号：US11908545B2
公开(公告)日：2024-02-20
申请号：US17679118
申请日：2022-02-24
发明人： Hidehiro Fujiwara , Haruki Mori , Wei-Chang Zhao
CPC分类号： G11C7/222 , G06F7/5443 , G11C7/106 , G11C7/1087 , G11C7/12
摘要： A memory device and an operating method for computing-in-memory (CIM) are provided. The memory device for CIM comprises a plurality of memory banks and a global multiply accumulate (MAC) circuit. Each of the memory banks comprises a first memory array, a first latch circuit, a second latch circuit and a local MAC circuit. The first latch circuit latches a first data from the first memory array in a first read cycle. The second latch circuit latches a second data from the first memory array in a second read cycle. The local MAC circuit performs a first stage CIM operation on a first latched data latched in the first latch circuit and the second latched data latched in the second latch circuit to provide a first stage CIM result. The global MAC circuit performs a second stage CIM operation on a plurality of first stage CIM results from the memory banks.
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公开(公告)号：US20230361081A1
公开(公告)日：2023-11-09
申请号：US17736971
申请日：2022-05-04
发明人： Hidehiro Fujiwara , Haruki Mori , Wei-Chang Zhao
CPC分类号： H01L25/0657 , H01L25/50 , G06N3/04 , H01L24/16 , H01L25/18 , H01L25/105 , H01L2224/16225 , H01L2224/16145 , H01L2924/1435 , H01L2225/06517 , H01L2225/06541 , H01L2225/1058
摘要： An in-memory computing circuit is provided. The in-memory computing circuit includes a core die, a plurality of conductive pillars, and a plurality of memory dies. The plurality of memory dies are coupled to the core die through the plurality of conductive pillars and are configured to implement computing operation. The plurality of memory dies includes at least one of the memory dies disposed on a bottommost memory die of the plurality of memory dies. The plurality of memory dies receives an input data from the core die through a common input terminal of the core die.
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公开(公告)号：US20210343317A1
公开(公告)日：2021-11-04
申请号：US17372540
申请日：2021-07-12
发明人： Hidehiro Fujiwara , Hsien-Yu Pan , Chih-Yu Lin , Yen-Huei Chen , Wei-Chang Zhao
IPC分类号： G11C5/06 , H01L27/11 , H01L27/092
摘要： A semiconductor chip is provided. The semiconductor chip includes a SRAM cell, a logic cell, a signal line and a ground line. The SRAM cell includes a storage transmission gate, a read transmission gate and a latch circuit. The latch circuit is serially connected between the storage and read transmission gates, and includes a first inverter, a second inverter and a transmission gate connected to an output of the first inverter, an input of the second inverter and an output of the storage transmission gate. The logic cell disposed aside the SRAM cell is connected with the SRAM cell by first and second active structures. The signal and ground lines extend at opposite sides of the SRAM and logic cells, and are substantially parallel with the first and second active structures. The SRAM and logic cells are disposed between and electrically connected to the signal and ground lines.
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公开(公告)号：US10892008B2
公开(公告)日：2021-01-12
申请号：US16434746
申请日：2019-06-07
发明人： Hidehiro Fujiwara , Hsien-Yu Pan , Chih-Yu Lin , Yen-Huei Chen , Wei-Chang Zhao
IPC分类号： G11C11/418
摘要： A memory macro system may be provided. The memory macro system may comprise a first segment, a second segment, a first WL, and a second WL. The first segment may comprise a first plurality of memory cells. The second segment may comprise a second plurality of memory cells. The first segment may be positioned over the second segment. The first WL may correspond to the first segment and the second WL may correspond to the second segment. The first WL and the second WL may be configured to be activated in one cycle.
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公开(公告)号：US11935586B2
公开(公告)日：2024-03-19
申请号：US17670384
申请日：2022-02-11
发明人： Hidehiro Fujiwara , Haruki Mori , Wei-Chang Zhao
IPC分类号： G11C11/417 , G06F7/544 , G11C11/412
CPC分类号： G11C11/417 , G06F7/5443 , G11C11/412
摘要： A memory device has a memory array of a plurality of memory cells arranged in a plurality of columns and a plurality of rows. The memory cells in each of the plurality of columns include first memory cells and second memory cells alternately arranged along a column direction of the plurality of columns. A first computation circuit is coupled to the first memory cells in each of the plurality of columns, and is configured to generate first output data corresponding to a first computation performed on first weight data stored in the first memory cells. A second computation circuit is coupled to the second memory cells in each of the plurality of columns, and is configured to generate second output data corresponding to a second computation performed on second weight data stored in the second memory cells.
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公开(公告)号：US20230377640A1
公开(公告)日：2023-11-23
申请号：US18321552
申请日：2023-05-22
发明人： Hidehiro Fujiwara , Hsien-Yu Pan , Chih-Yu Lin , Yen-Huei Chen , Wei-Chang Zhao
IPC分类号： G11C11/419 , H01L27/02 , G11C11/412 , H10B10/00
CPC分类号： G11C11/419 , H01L27/0207 , G11C11/412 , H10B10/12
摘要： A memory cell includes a write port and a read port. The write port includes two cross-coupled inverters that form a storage unit. The cross-coupled inverters are connected between a first power source signal line and a second power source signal line. The write port also includes a first local interconnect line in an interconnect layer that is connected to the second power source signal line. The read port includes a transistor that is connected to the storage unit in the write port and to the second power source signal line, and a second local interconnect line in the interconnect layer that is connected to the second power source signal line. The second local interconnect line in the read port is separate from the first local interconnect line in the write port.
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公开(公告)号：US20220244916A1
公开(公告)日：2022-08-04
申请号：US17387598
申请日：2021-07-28
发明人： Po-Hao Lee , Chia-Fu Lee , Yi-Chun Shih , Yu-Der Chih , Hidehiro Fujiwara , Haruki Mori , Wei-Chang Zhao
IPC分类号： G06F7/544
摘要： A compute-in-memory (CIM) device has a memory array with a plurality of memory cells arranged in rows and columns. The plurality of memory cells includes a first memory cell in a first row and a first column of the memory array and a second memory cell in the first row and a second column of the memory array. The first and second memory cells are configured to store respective first and second weight signals. An input driver provides a plurality of input signals. A first logic circuit is coupled to the first memory cell to provide a first output signal based on a first input signal from the input driver and the first weight signal. A second logic circuit is coupled to the second memory cell to provide a second output signal based on a second input signal from the input driver and the second weight signal.
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公开(公告)号：US20210350849A1
公开(公告)日：2021-11-11
申请号：US17381234
申请日：2021-07-21
发明人： Hidehiro Fujiwara , Hsien-Yu Pan , Chih-Yu Lin , Yen-Huei Chen , Wei-Chang Zhao
IPC分类号： G11C11/419 , H01L27/02 , H01L27/11 , G11C11/412
摘要： A memory cell includes a write port and a read port. The write port includes two cross-coupled inverters that form a storage unit. The cross-coupled inverters are connected between a first power source signal line and a second power source signal line. The write port also includes a first local interconnect line in an interconnect layer that is connected to the second power source signal line. The read port includes a transistor that is connected to the storage unit in the write port and to the second power source signal line, and a second local interconnect line in the interconnect layer that is connected to the second power source signal line. The second local interconnect line in the read port is separate from the first local interconnect line in the write port.
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公开(公告)号：US20210098054A1
公开(公告)日：2021-04-01
申请号：US17120640
申请日：2020-12-14
发明人： Hidehiro Fujiwara , Hsien-Yu Pan , Chih-Yu Lin , Yen-Huei Chen , Wei-Chang Zhao
IPC分类号： G11C11/418
摘要： A memory macro system may be provided. The memory macro system may comprise a first segment, a second segment, a first WL, and a second WL. The first segment may comprise a first plurality of memory cells. The second segment may comprise a second plurality of memory cells. The first segment may be positioned over the second segment. The first WL may correspond to the first segment and the second WL may correspond to the second segment. The first WL and the second WL may be configured to be activated in one cycle.
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公开(公告)号：US20230315389A1
公开(公告)日：2023-10-05
申请号：US17855089
申请日：2022-06-30
发明人： Hidehiro Fujiwara , Haruki Mori , Wei-Chang Zhao , Chia-Fu Lee , Nail Etkin Can AKKAYA , Mahmut Sinangil
IPC分类号： G06F7/57
CPC分类号： G06F7/57 , G11C11/401
摘要： A device includes a first memory cell, a second memory cell, a first logic element, a second logic element, and a third logic element. The first memory cell is configured to store a first bit at a first node, and the second memory cell is configured to store a second bit at a second node. The first logic element includes a first node input terminal coupled to the first node, the second logic element includes a second node input terminal coupled to the second node, and the third logic element includes a first input terminal coupled to a first output terminal of the first logic element and a second input terminal coupled to a second output terminal of the second logic element.
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