公开(公告)号：US20240014180A1

公开(公告)日：2024-01-11

申请号：US18471326

申请日：2023-09-21

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Kuei Hsu ,  Feng-Cheng Hsu ,  Ming-Chih Yew ,  Po-Yao Lin ,  Shuo-Mao Chen ,  Shin-Puu Jeng

IPC: H01L25/065 ,  H01L21/50 ,  H01L21/768 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L21/50 ,  H01L21/768 ,  H01L23/31 ,  H01L23/5386 ,  H01L24/14 ,  H01L2224/0401

Abstract: A semiconductor package includes a semiconductor die, a redistribution circuit structure, a supporting structure and a protective layer. The redistribution circuit structure is located on and electrically coupled to the semiconductor die. The supporting structure is located on an outer surface of the redistribution circuit structure, wherein the supporting structure is overlapped with at least a part of the semiconductor die or has a sidewall substantially aligned with a sidewall of the semiconductor die in a vertical projection on the redistribution circuit structure along a stacking direction of the redistribution circuit structure and the supporting structure. The protective layer is located on the supporting structure, wherein the supporting structure is sandwiched between the protective layer and the redistribution circuit structure.

公开(公告)号：US11675957B2

公开(公告)日：2023-06-13

申请号：US17319687

申请日：2021-05-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Feng Wei Kuo ,  Shuo-Mao Chen ,  Chin-Yuan Huang ,  Kai-Yun Lin ,  Ho-Hsiang Chen ,  Chewn-Pu Jou

IPC: G06F30/398 ,  H01L23/544 ,  H01L25/07

CPC classification number: G06F30/398 ,  H01L23/544 ,  H01L25/07 ,  H01L2223/54426

Abstract: A method of verifying an integrated circuit stack includes adding a dummy layer to a contact pad of a functional circuit, wherein a location of the dummy layer is determined based on a location of a contact pad of a connecting substrate. The method further includes converting the dummy layer location to the connecting substrate. The method further includes performing a layout versus schematic (LVS) check of the connecting substrate including the dummy layer in response to a determination that the dummy layer is aligned with the contact pad of the connecting substrate.

公开(公告)号：US20230067914A1

公开(公告)日：2023-03-02

申请号：US17462000

申请日：2021-08-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Meng-Liang Lin ,  Po-Yao Chuang ,  Te-Chi Wong ,  Shuo-Mao Chen ,  Shin-Puu Jeng

IPC: H01L23/31 ,  H01L23/48 ,  H01L21/56 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes at least a circuit substrate, a semiconductor die and a filling material. The circuit substrate has a first surface, a second surface opposite to the first surface and a cavity concave from the first surface. The circuit substrate includes a dielectric material and a metal floor plate embedded in the dielectric material and located below the cavity. A location of the metal floor plate corresponds to a location of the cavity. The metal floor plate is electrically floating and isolated by the dielectric material. The semiconductor die is disposed in the cavity and electrically connected with the circuit substrate. The filling material is disposed between the semiconductor die and the circuit substrate. The filling material fills the cavity and encapsulates the semiconductor die to attach the semiconductor die and the circuit substrate.

公开(公告)号：US11469208B2

公开(公告)日：2022-10-11

申请号：US17017543

申请日：2020-09-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Shin-Puu Jeng ,  Feng-Cheng Hsu ,  Shuo-Mao Chen

IPC: H01L25/065 ,  H01L21/683 ,  H01L25/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00

Abstract: A semiconductor package structure includes a redistribution (RDL) layer, a first chip, at least one second chip, an encapsulant and a third chip. The redistribution layer has a first surface and a second surface opposite to each other. The first chip is over the first surface of the redistribution layer and electrically connected to the redistribution layer. The second chip is over the first surface of the redistribution layer. The second chip includes a plurality of through via structures. The encapsulant is over the first surface of the distribution layer, wherein the encapsulant surrounds the first chip and the second chip. The third chip is over the encapsulant and electrically connected to the first chip through the through via structures of the second chip and the redistribution layer.

公开(公告)号：US20220302081A1

公开(公告)日：2022-09-22

申请号：US17206098

申请日：2021-03-18

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Kuei Hsu ,  Feng-Cheng Hsu ,  Ming-Chih Yew ,  Po-Yao Lin ,  Shuo-Mao Chen ,  Shin-Puu Jeng

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L21/50 ,  H01L21/768

Abstract: A semiconductor package includes a semiconductor die, a redistribution circuit structure, a supporting structure and a protective layer. The redistribution circuit structure is located on and electrically coupled to the semiconductor die. The supporting structure is located on an outer surface of the redistribution circuit structure, wherein the supporting structure is overlapped with at least a part of the semiconductor die or has a sidewall substantially aligned with a sidewall of the semiconductor die in a vertical projection on the redistribution circuit structure along a stacking direction of the redistribution circuit structure and the supporting structure. The protective layer is located on the supporting structure, wherein the supporting structure is sandwiched between the protective layer and the redistribution circuit structure.

公开(公告)号：US20220223533A1

公开(公告)日：2022-07-14

申请号：US17708666

申请日：2022-03-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Feng Wei Kuo ,  Chewn-Pu Jou ,  Shuo-Mao Chen

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  G02B6/42 ,  H01L23/498 ,  H01L25/00 ,  H01L21/56 ,  H01L21/48 ,  H01L21/683 ,  H01L25/18

Abstract: An integrated circuit package integrates a photonic die (oDie) and an electronic die (eDie). More specifically, the integrated circuit package may include a plurality of redistribution layers communicatively coupled to at least one of the oDie and/or the eDie, where molded material at least partially surrounds the at least one of the oDie and/or the eDie.

公开(公告)号：US11315878B2

公开(公告)日：2022-04-26

申请号：US16654679

申请日：2019-10-16

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Feng Wei Kuo ,  Chewn-Pu Jou ,  Shuo-Mao Chen

IPC: H01L23/538 ,  G02B6/42 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L25/18 ,  H01L25/00 ,  H01L25/16

Abstract: An integrated circuit package integrates a photonic die (oDie) and an electronic die (eDie). More specifically, the integrated circuit package may include a plurality of redistribution layers communicatively coupled to at least one of the oDie and/or the eDie, where molded material at least partially surrounds the at least one of the oDie and/or the eDie.

公开(公告)号：US20210296220A1

公开(公告)日：2021-09-23

申请号：US16823995

申请日：2020-03-19

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Kuei Hsu ,  Ming-Chih Yew ,  Po-Yao Lin ,  Shuo-Mao Chen ,  Feng-Cheng Hsu ,  Shin-Puu Jeng

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L21/56 ,  H01L25/065 ,  H01L25/18

Abstract: A method includes forming a redistribution structure, which formation process includes forming a plurality of dielectric layers over a carrier, forming a plurality of redistribution lines extending into the plurality of dielectric layers, and forming a reinforcing patch over the carrier. The method further includes bonding a package component to the redistribution structure, with the package component having a peripheral region overlapping a portion of the reinforcing patch. And de-bonding the redistribution structure and the first package component from the carrier.

公开(公告)号：US11023647B2

公开(公告)日：2021-06-01

申请号：US15921040

申请日：2018-03-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Feng Wei Kuo ,  Shuo-Mao Chen ,  Chin-Yuan Huang ,  Kai-Yun Lin ,  Ho-Hsiang Chen ,  Chewn-Pu Jou

IPC: G06F30/398 ,  H01L23/544 ,  H01L25/07

Abstract: A method of verifying an integrated circuit stack includes adding a dummy layer to a contact pad of a functional circuit, wherein a location of the dummy layer is determined based on a location of a contact pad of a connecting substrate. The method further includes converting the dummy layer location to the connecting substrate. The method further includes determining whether the dummy layer is aligned with the contact pad of the connecting substrate. The method further includes adjusting the dummy layer location in the functional circuit when the dummy layer location is misaligned with the contact pad of the connecting substrate.

公开(公告)号：US10741537B2

公开(公告)日：2020-08-11

申请号：US15725766

申请日：2017-10-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Hsiang-Tai Lu ,  Shuo-Mao Chen ,  Mill-Jer Wang ,  Feng-Cheng Hsu ,  Chao-Hsiang Yang ,  Shin-Puu Jeng ,  Cheng-Yi Hong ,  Chih-Hsien Lin ,  Dai-Jang Chen ,  Chen-Hua Lin

IPC: H01L25/00 ,  H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L25/10 ,  H01L21/48 ,  H01L21/56 ,  H01L21/66 ,  H01L23/498 ,  H01L23/522 ,  H01L23/053

Abstract: A method of manufacturing a semiconductor structure includes forming a redistribution layer (RDL); forming a conductive member over the RDL; performing a first electrical test through the conductive member; disposing a first die over the RDL; performing a second electrical test through the conductive member; and disposing a second die over the first die and the conductive member.