公开(公告)号：USD615545S1

公开(公告)日：2010-05-11

申请号：US29315452

申请日：2009-06-26

申请人： Susumu Inoue ,  Koichi Kikuchi ,  Shinsuke Kogi

设计人： Susumu Inoue ,  Koichi Kikuchi ,  Shinsuke Kogi

公开(公告)号：USD614189S1

公开(公告)日：2010-04-20

申请号：US29315448

申请日：2009-06-26

申请人： Susumu Inoue ,  Koichi Kikuchi ,  Shinsuke Kogi

设计人： Susumu Inoue ,  Koichi Kikuchi ,  Shinsuke Kogi

公开(公告)号：US20100110271A1

公开(公告)日：2010-05-06

申请号：US12604523

申请日：2009-10-23

申请人： Takeshi Yanagita ,  Keiji Mabuchi ,  Susumu Inoue

发明人： Takeshi Yanagita ,  Keiji Mabuchi ,  Susumu Inoue

IPC分类号： H04N5/225 ,  H01L31/0232 ,  H01L21/00

CPC分类号： H01L27/14623 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/1464 ,  H01L27/14643

摘要： A solid-state imaging device includes an effective pixel portion in which a plurality of pixels including photoelectric conversion elements are arrayed; and a nonconductive interpixel light-shielding film that is placed in the effective pixel portion and that shields areas between the pixels.

摘要翻译： 一种固态成像装置，包括排列具有光电转换元件的多个像素的有效像素部， 以及放置在有效像素部分中并遮蔽像素之间的区域的非导电像素间屏蔽膜。

公开(公告)号：US20080283728A1

公开(公告)日：2008-11-20

申请号：US12081531

申请日：2008-04-17

申请人： Susumu Inoue

发明人： Susumu Inoue

IPC分类号： H01L27/00 ,  H01L21/00

CPC分类号： H01L27/14627 ,  H01L27/14625 ,  H01L27/14629 ,  H01L27/1463 ,  H01L27/14636 ,  H04N9/045

摘要： Disclosed herein is a solid-state image pickup device, including: a first pixel for receiving a visible light of an incident light to subject the visible light to photoelectric conversion; a second pixel for receiving the visible light and a near-infrared light of the incident light to subject each of the visible light and the near-infrared light to the photoelectric conversion; a color filter layer; and an infrared light filter layer for absorbing or reflecting an infrared light, and transmitting the visible light.

摘要翻译： 本文公开了一种固态图像拾取装置，包括：第一像素，用于接收入射光的可见光以对可见光进行光电转换; 用于接收可见光的第二像素和入射光的近红外光，以使每个可见光和近红外光进行光电转换; 滤色器层; 以及用于吸收或反射红外光的红外光滤光层，并透射可见光。

公开(公告)号：US07304337B2

公开(公告)日：2007-12-04

申请号：US11287710

申请日：2005-11-28

申请人： Susumu Inoue ,  Yo Takeda ,  Yutaka Maruo

发明人： Susumu Inoue ,  Yo Takeda ,  Yutaka Maruo

IPC分类号： H01L31/062 ,  H01L31/113 ,  H01L29/06 ,  H01L31/0328 ,  H01L31/0336

CPC分类号： H01L31/02164 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11558 ,  H01L27/14623 ,  H01L29/66825 ,  H01L29/788

摘要： A semiconductor device includes: a semiconductor element provided on a semiconductor layer; a light-blocking wall provided around the semiconductor element; and a wiring layer electrically coupled to the semiconductor element and extended from an aperture not having the light-blocking wall to an outside of the light-blocking wall; wherein the wiring layer has a pattern containing a first section positioned in the aperture and a second section which has a width not narrower than a width of the aperture by providing a branched portion intersecting with an extension direction of the wiring layer; and wherein a surface of the branched portion facing outside of the light-blocking wall includes thereon a convex part.

摘要翻译： 半导体器件包括：设置在半导体层上的半导体元件; 设置在半导体元件周围的遮光壁; 以及布线层，其电耦合到所述半导体元件并且从不具有所述遮光壁的孔延伸到所述遮光壁的外部; 其中所述布线层具有包含定位在所述孔中的第一部分的图案和通过提供与所述布线层的延伸方向相交的分支部分而具有不窄于所述孔宽度的宽度的第二部分; 并且其中所述分支部分的面向所述遮光壁外侧的表面包括凸起部分。

公开(公告)号：US20060273373A1

公开(公告)日：2006-12-07

申请号：US11422404

申请日：2006-06-06

申请人： Susumu Inoue ,  Yutaka Maruo

发明人： Susumu Inoue ,  Yutaka Maruo

IPC分类号： H01L29/788

CPC分类号： H01L29/7883 ,  H01L27/11558 ,  H01L29/40114 ,  H01L29/42324 ,  H01L29/66825

摘要： A semiconductor device, includes: a non-volatile memory element, wherein the non-volatile memory element includes: a first region; a second region formed adjacent to the first region; and a third region formed adjacent to the second region; and the non-volatile memory element includes: a semiconductor layer; an isolation insulating layer provided on the semiconductor layer and defines a forming region of the non-volatile memory element; a first diffused layer formed on the semiconductor layer in the first region; a first source region and a first drain region formed on the first diffused layer; a second diffused layer spaced apart from the first diffused layer and formed on the semiconductor layer at a periphery of the first diffused layer and the second region; a third diffused layer formed on the semiconductor layer in the third region; a second source region and a second drain region formed on the third diffused layer; a first insulating layer formed above the semiconductor layer in the forming region of the non-volatile memory element; and a first conductive layer provided above the first insulating layer.

摘要翻译： 一种半导体器件，包括：非易失性存储元件，其中所述非易失性存储元件包括：第一区域; 与所述第一区域相邻形成的第二区域; 以及与所述第二区域相邻形成的第三区域; 并且所述非易失性存储元件包括：半导体层; 隔离绝缘层，设置在所述半导体层上并限定所述非易失性存储元件的形成区域; 在所述第一区域中形成在所述半导体层上的第一扩散层; 形成在第一扩散层上的第一源区和第一漏区; 与第一扩散层间隔开并形成在第一扩散层和第二区域的周边的半导体层上的第二扩散层; 第三扩散层，形成在所述第三区域中的所述半导体层上; 形成在第三扩散层上的第二源区和第二漏区; 在所述非易失性存储元件的形成区域中形成在所述半导体层上方的第一绝缘层; 以及设置在第一绝缘层上方的第一导电层。

公开(公告)号：US20060131623A1

公开(公告)日：2006-06-22

申请号：US11287710

申请日：2005-11-28

申请人： Susumu Inoue ,  Yo Takeda ,  Yutaka Maruo

发明人： Susumu Inoue ,  Yo Takeda ,  Yutaka Maruo

IPC分类号： H01L31/113

CPC分类号： H01L31/02164 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11558 ,  H01L27/14623 ,  H01L29/66825 ,  H01L29/788

摘要： A semiconductor device includes: a semiconductor element provided on a semiconductor layer; a light-blocking wall provided around the semiconductor element; and a wiring layer electrically coupled to the semiconductor element and extended from an aperture not having the light-blocking wall to an outside of the light-blocking wall; wherein the wiring layer has a pattern containing a first section positioned in the aperture and a second section which has a width not narrower than a width of the aperture by providing a branched portion intersecting with an extension direction of the wiring layer; and wherein a surface of the branched portion facing outside of the light-blocking wall includes thereon a convex part.

摘要翻译： 半导体器件包括：设置在半导体层上的半导体元件; 设置在半导体元件周围的遮光壁; 以及布线层，其电耦合到所述半导体元件并且从不具有所述遮光壁的孔延伸到所述遮光壁的外部; 其中所述布线层具有包含定位在所述孔中的第一部分的图案和通过提供与所述布线层的延伸方向相交的分支部分而具有不窄于所述孔宽度的宽度的第二部分; 并且其中所述分支部分的面向所述遮光壁外侧的表面包括凸起部分。

公开(公告)号：US07008850B2

公开(公告)日：2006-03-07

申请号：US10962111

申请日：2004-10-07

申请人： Takafumi Noda ,  Susumu Inoue ,  Masahiko Tsuyuki ,  Akihiko Ebina

发明人： Takafumi Noda ,  Susumu Inoue ,  Masahiko Tsuyuki ,  Akihiko Ebina

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L21/76

CPC分类号： H01L21/823857 ,  H01L21/76202 ,  H01L21/76224 ,  H01L21/823814

摘要： A method for manufacturing the semiconductor device of which a transistor and a MNOS type memory transistor, each of which has a different gate withstand voltage and drain withstand voltage, are included in the same semiconductor layer.

摘要翻译： 制造其半导体器件的方法包括在同一半导体层中，其晶体管和MNOS型存储晶体管具有不同的栅极耐受电压和漏极耐受电压。

公开(公告)号：US06989305B2

公开(公告)日：2006-01-24

申请号：US10636582

申请日：2003-08-08

申请人： Susumu Inoue

发明人： Susumu Inoue

IPC分类号： H01L21/8247

CPC分类号： H01L27/11568 ,  H01L27/115 ,  Y10S438/954

摘要： A method of manufacturing a semiconductor device including a memory region in which non-volatile memory devices are arranged in a matrix form of a plurality of rows and a plurality of columns to form a memory cell array, the method including the steps of: forming a gate insulation layer, a conductive layer that will form a word gate, and a stopper layer above a semiconductor layer; forming a first insulation layer over the entire surface of the memory region; forming a first control gate in the form of a side wall on each of both side surfaces of the word gate, with the first insulation layer interposed with respect to the semiconductor layer; etching the surface of the first control gate; using that first control gate as a mask to remove part of the first insulation layer, thus forming a second insulation layer; forming a third conductive layer over the entire surface of the memory region; and forming a second control gate on the side surface of the first control gate, with the second insulation layer interposed with respect to the semiconductor layer, by anisotropic etching of the third conductive layer.

摘要翻译： 一种制造半导体器件的方法，该半导体器件包括存储区域，其中非易失性存储器件以多行和多列的矩阵形式排列以形成存储单元阵列，该方法包括以下步骤：形成 栅极绝缘层，将形成字栅的导电层和半导体层上方的阻挡层; 在所述存储区域的整个表面上形成第一绝缘层; 在所述字栅的两个侧表面中的每一个上形成侧壁形式的第一控制栅极，所述第一绝缘层相对于所述半导体层插入; 蚀刻第一控制栅极的表面; 使用该第一控制栅极作为掩模去除第一绝缘层的一部分，从而形成第二绝缘层; 在所述存储区的整个表面上形成第三导电层; 以及通过所述第三导电层的各向异性蚀刻，在所述第一控制栅极的侧表面上形成第二控制栅极，所述第二绝缘层相对于所述半导体层插入。

公开(公告)号：US20050032312A1

公开(公告)日：2005-02-10

申请号：US10939330

申请日：2004-09-14

申请人： Akihiko Ebina ,  Susumu Inoue

发明人： Akihiko Ebina ,  Susumu Inoue

IPC分类号： H01L21/8247 ,  H01L21/8234 ,  H01L21/8246 ,  H01L27/088 ,  H01L27/10 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/82 ,  H01L21/336

CPC分类号： H01L27/11568 ,  H01L27/105 ,  H01L27/11573

摘要： A semiconductor device having memory cells. Each of the memory cells has a word gate formed over a semiconductor substrate with a first gate insulating layer interposed, an impurity layer, and first and second control gates in the shape of sidewalls. The first and second control gates adjacent to each other with the impurity layer interposed are connected to a common contact section. The common contact section includes a first contact conductive layer, a second contact conductive layer, and a pad-shaped third contact conductive layer. The third contact conductive layer is formed over the first and second contact conductive layers.