公开(公告)号：US07667249B2

公开(公告)日：2010-02-23

申请号：US11977333

申请日：2007-10-24

申请人： Susumu Inoue ,  Yo Takeda ,  Yutaka Maruo

发明人： Susumu Inoue ,  Yo Takeda ,  Yutaka Maruo

IPC分类号： H01L31/062 ,  H01L31/113 ,  H01L29/06 ,  H01L31/072 ,  H01L31/0328

CPC分类号： H01L31/02164 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11558 ,  H01L27/14623 ,  H01L29/66825 ,  H01L29/788

摘要： A semiconductor device includes: a semiconductor element provided on a semiconductor layer; a light-blocking wall provided around the semiconductor element; and a wiring layer electrically coupled to the semiconductor element and extended from an aperture not having the light-blocking wall to an outside of the light-blocking wall; wherein the wiring layer has a pattern containing a first section positioned in the aperture and a second section which has a width not narrower than a width of the aperture by providing a branched portion intersecting with an extension direction of the wiring layer; and wherein a surface of the branched portion facing outside of the light-blocking wall includes thereon a convex part.

摘要翻译： 半导体器件包括：设置在半导体层上的半导体元件; 设置在半导体元件周围的遮光壁; 以及布线层，其电耦合到所述半导体元件并且从不具有所述遮光壁的孔延伸到所述遮光壁的外部; 其中所述布线层具有包含定位在所述孔中的第一部分的图案和通过提供与所述布线层的延伸方向相交的分支部分而具有不窄于所述孔宽度的宽度的第二部分; 并且其中所述分支部分的面向所述遮光壁外侧的表面包括凸起部分。

公开(公告)号：US20080067564A1

公开(公告)日：2008-03-20

申请号：US11977333

申请日：2007-10-24

申请人： Susumu Inoue ,  Yo Takeda ,  Yutaka Maruo

发明人： Susumu Inoue ,  Yo Takeda ,  Yutaka Maruo

IPC分类号： H01L31/113

CPC分类号： H01L31/02164 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11558 ,  H01L27/14623 ,  H01L29/66825 ,  H01L29/788

摘要： A semiconductor device includes: a semiconductor element provided on a semiconductor layer; a light-blocking wall provided around the semiconductor element; and a wiring layer electrically coupled to the semiconductor element and extended from an aperture not having the light-blocking wall to an outside of the light-blocking wall; wherein the wiring layer has a pattern containing a first section positioned in the aperture and a second section which has a width not narrower than a width of the aperture by providing a branched portion intersecting with an extension direction of the wiring layer; and wherein a surface of the branched portion facing outside of the light-blocking wall includes thereon a convex part.

摘要翻译： 半导体器件包括：设置在半导体层上的半导体元件; 设置在半导体元件周围的遮光壁; 以及布线层，其电耦合到所述半导体元件并且从不具有所述遮光壁的孔延伸到所述遮光壁的外部; 其中所述布线层具有包含定位在所述孔中的第一部分的图案和通过提供与所述布线层的延伸方向相交的分支部分而具有不窄于所述孔宽度的宽度的第二部分; 并且其中所述分支部分的面向所述遮光壁外侧的表面包括凸起部分。

公开(公告)号：US07126175B2

公开(公告)日：2006-10-24

申请号：US11288458

申请日：2005-11-29

申请人： Susumu Inoue ,  Yo Takeda ,  Yutaka Maruo

发明人： Susumu Inoue ,  Yo Takeda ,  Yutaka Maruo

IPC分类号： H01L31/062 ,  H01L31/113

CPC分类号： H01L23/552 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device comprising: a first light shielded region including a first semiconductor element, the first light shielded region being defined by a first light shielding wall provided in the periphery thereof; a second light shielded region including a second semiconductor element, the second light shielded region being defined by a second light shielding wall provided in the periphery thereof and being provided in a position adjacent to the first light shielded region; a first opening provided in the first light shielding wall; a second opening provided in the second light shielding wall and positioned facing to the first opening; a first wiring layer coupled with the first semiconductor element and brought out to the outside of the first light shielded region from the first opening; a second wiring layer coupled with the second semiconductor element and brought out to the outside of the second light shielded region from the second opening; and a light shielding film provided at least above a region sandwiched between the first light shielded region and the second light shielded region.

摘要翻译： 一种半导体器件，包括：包括第一半导体元件的第一遮光区域，所述第一遮光区域由设置在其周边的第一遮光壁限定; 第二遮光区域，包括第二半导体元件，所述第二遮光区域由设置在其周边的第二遮光壁限定，并且设置在与所述第一遮光区域相邻的位置; 设置在第一遮光壁上的第一开口; 第二开口，设置在所述第二遮光壁上并且面向所述第一开口定位; 与所述第一半导体元件耦合并从所述第一开口导出到所述第一遮光区域的外部的第一布线层; 与所述第二半导体元件耦合并从所述第二开口导出到所述第二遮光区域的外部的第二布线层; 以及设置在夹在第一遮光区域和第二遮光区域之间的区域的至少上方的遮光膜。

公开(公告)号：US07304337B2

公开(公告)日：2007-12-04

申请号：US11287710

申请日：2005-11-28

申请人： Susumu Inoue ,  Yo Takeda ,  Yutaka Maruo

发明人： Susumu Inoue ,  Yo Takeda ,  Yutaka Maruo

IPC分类号： H01L31/062 ,  H01L31/113 ,  H01L29/06 ,  H01L31/0328 ,  H01L31/0336

CPC分类号： H01L31/02164 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11558 ,  H01L27/14623 ,  H01L29/66825 ,  H01L29/788

摘要： A semiconductor device includes: a semiconductor element provided on a semiconductor layer; a light-blocking wall provided around the semiconductor element; and a wiring layer electrically coupled to the semiconductor element and extended from an aperture not having the light-blocking wall to an outside of the light-blocking wall; wherein the wiring layer has a pattern containing a first section positioned in the aperture and a second section which has a width not narrower than a width of the aperture by providing a branched portion intersecting with an extension direction of the wiring layer; and wherein a surface of the branched portion facing outside of the light-blocking wall includes thereon a convex part.

摘要翻译： 半导体器件包括：设置在半导体层上的半导体元件; 设置在半导体元件周围的遮光壁; 以及布线层，其电耦合到所述半导体元件并且从不具有所述遮光壁的孔延伸到所述遮光壁的外部; 其中所述布线层具有包含定位在所述孔中的第一部分的图案和通过提供与所述布线层的延伸方向相交的分支部分而具有不窄于所述孔宽度的宽度的第二部分; 并且其中所述分支部分的面向所述遮光壁外侧的表面包括凸起部分。

公开(公告)号：US20060131623A1

公开(公告)日：2006-06-22

申请号：US11287710

申请日：2005-11-28

申请人： Susumu Inoue ,  Yo Takeda ,  Yutaka Maruo

发明人： Susumu Inoue ,  Yo Takeda ,  Yutaka Maruo

IPC分类号： H01L31/113

CPC分类号： H01L31/02164 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11558 ,  H01L27/14623 ,  H01L29/66825 ,  H01L29/788

摘要： A semiconductor device includes: a semiconductor element provided on a semiconductor layer; a light-blocking wall provided around the semiconductor element; and a wiring layer electrically coupled to the semiconductor element and extended from an aperture not having the light-blocking wall to an outside of the light-blocking wall; wherein the wiring layer has a pattern containing a first section positioned in the aperture and a second section which has a width not narrower than a width of the aperture by providing a branched portion intersecting with an extension direction of the wiring layer; and wherein a surface of the branched portion facing outside of the light-blocking wall includes thereon a convex part.

摘要翻译： 半导体器件包括：设置在半导体层上的半导体元件; 设置在半导体元件周围的遮光壁; 以及布线层，其电耦合到所述半导体元件并且从不具有所述遮光壁的孔延伸到所述遮光壁的外部; 其中所述布线层具有包含定位在所述孔中的第一部分的图案和通过提供与所述布线层的延伸方向相交的分支部分而具有不窄于所述孔宽度的宽度的第二部分; 并且其中所述分支部分的面向所述遮光壁外侧的表面包括凸起部分。

公开(公告)号：US07508019B2

公开(公告)日：2009-03-24

申请号：US11768589

申请日：2007-06-26

申请人： Susumu Inoue ,  Yo Takeda ,  Yutaka Maruo

发明人： Susumu Inoue ,  Yo Takeda ,  Yutaka Maruo

IPC分类号： H01L31/113

CPC分类号： H01L31/02164 ,  H01L23/552 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11558 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a semiconductor element that is set up on a semiconductor layer, a light shielding wall that is set up around the semiconductor element, a hole that is set up on the light shielding wall, and a wiring layer that is electrically connected to the semiconductor element and is drawn out through the hole to the outside of the light shielding wall. The wiring layer has a pattern including a first part that is located within the hole and a second part that is located on the outside of the hole and has a larger width compared to the width of the first part, the width of the second part being the same with or larger than the width of the hole.

摘要翻译： 一种半导体器件包括设置在半导体层上的半导体元件，围绕半导体元件设置的遮光壁，设置在遮光壁上的孔，以及电连接到 半导体元件并且通过孔被拉出到遮光壁的外部。 布线层具有图案，其包括位于孔内的第一部分和位于孔的外侧的第二部分，并且与第一部分的宽度相比具有较大的宽度，第二部分的宽度为 与孔的宽度相同或大于孔的宽度。

公开(公告)号：US07482647B2

公开(公告)日：2009-01-27

申请号：US11768514

申请日：2007-06-26

申请人： Susumu Inoue ,  Yo Takeda ,  Yutaka Maruo

发明人： Susumu Inoue ,  Yo Takeda ,  Yutaka Maruo

IPC分类号： H01L31/113

CPC分类号： H01L31/02164 ,  H01L23/552 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11558 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a semiconductor element that is set up on a semiconductor layer, a light shielding wall that is set up around the semiconductor element, a hole that is set up on the light shielding wall, and a wiring layer that is electrically connected to the semiconductor element and is drawn out through the hole to the outside of the light shielding wall. The wiring layer has a pattern including a first part that is located within the hole and a second part that is located on the outside of the hole and has a larger width compared to the width of the first part, the width of the second part being the same with or larger than the width of the hole.

公开(公告)号：US07473962B2

公开(公告)日：2009-01-06

申请号：US11330870

申请日：2006-01-12

申请人： Yutaka Maruo ,  Susumu Inoue ,  Yo Takeda

发明人： Yutaka Maruo ,  Susumu Inoue ,  Yo Takeda

IPC分类号： H01L29/94

CPC分类号： H01L27/11521 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11541 ,  H01L27/11543 ,  H01L27/11558

摘要： A semiconductor device includes: a semiconductor layer; a first area and a second area which are demarcated by a separation insulating layer provided on the semiconductor layer; a nonvolatile memory provided on the first area; a plurality of MOS transistors provided on the second area; a first interlayer insulating layer embedded between the plurality of MOS transistors on the second area; and a second interlayer insulating layer provided above the first area and the second area. The second interlayer insulating layer is provided as if covering the nonvolatile memory on the first area and, on the second area, provided, being above the first interlayer insulating layer, as if covering the MOS transistor.

摘要翻译： 半导体器件包括：半导体层; 第一区域和第二区域，其由设置在所述半导体层上的分离绝缘层划定; 设置在所述第一区域上的非易失性存储器; 设置在所述第二区域上的多个MOS晶体管; 嵌入在所述第二区域上的所述多个MOS晶体管之间的第一层间绝缘层; 以及设置在所述第一区域和所述第二区域上方的第二层间绝缘层。 第二层间绝缘层被设置为如同覆盖第一区域上的非易失性存储器，并且在第二区域上设置在第一层间绝缘层的上方，就像覆盖MOS晶体管一样。

公开(公告)号：US07253462B2

公开(公告)日：2007-08-07

申请号：US11249253

申请日：2005-10-13

申请人： Susumu Inoue ,  Yo Takeda ,  Yutaka Maruo

发明人： Susumu Inoue ,  Yo Takeda ,  Yutaka Maruo

IPC分类号： H01L31/113

CPC分类号： H01L31/02164 ,  H01L23/552 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11558 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a semiconductor element that is set up on a semiconductor layer, a light shielding wall that is set up around the semiconductor element, a hole that is set up on the light shielding wall, and a wiring layer that is electrically connected to the semiconductor element and is drawn out through the hole to the outside of the light shielding wall. The wiring layer has a pattern including a first part that is located within the hole and a second part that is located on the outside of the hole and has a larger width compared to the width of the first part, the width of the second part being the same with or larger than the width of the hole.

摘要翻译： 一种半导体器件包括设置在半导体层上的半导体元件，围绕半导体元件设置的遮光壁，设置在遮光壁上的孔，以及电连接到 半导体元件并且通过孔被拉出到遮光壁的外部。 布线层具有图案，其包括位于孔内的第一部分和位于孔的外侧的第二部分，并且与第一部分的宽度相比具有较大的宽度，第二部分的宽度为 与孔的宽度相同或大于孔的宽度。

公开(公告)号：US20060170030A1

公开(公告)日：2006-08-03

申请号：US11330870

申请日：2006-01-12

申请人： Yutaka Maruo ,  Susumu Inoue ,  Yo Takeda

发明人： Yutaka Maruo ,  Susumu Inoue ,  Yo Takeda

IPC分类号： H01L29/788

CPC分类号： H01L27/11521 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11541 ,  H01L27/11543 ,  H01L27/11558

摘要： A semiconductor device includes: a semiconductor layer; a first area and a second area which are demarcated by a separation insulating layer provided on the semiconductor layer; a nonvolatile memory provided on the first area; a plurality of MOS transistors provided on the second area; a first interlayer insulating layer embedded between the plurality of MOS transistors on the second area; and a second interlayer insulating layer provided above the first area and the second area. The second interlayer insulating layer is provided as if covering the nonvolatile memory on the first area and, on the second area, provided, being above the first interlayer insulating layer, as if covering the MOS transistor.

摘要翻译： 半导体器件包括：半导体层; 第一区域和第二区域，其由设置在所述半导体层上的分离绝缘层划定; 设置在所述第一区域上的非易失性存储器; 设置在所述第二区域上的多个MOS晶体管; 嵌入在所述第二区域上的所述多个MOS晶体管之间的第一层间绝缘层; 以及设置在所述第一区域和所述第二区域上方的第二层间绝缘层。 第二层间绝缘层被设置为如同覆盖第一区域上的非易失性存储器，并且在第二区域上设置在第一层间绝缘层的上方，就像覆盖MOS晶体管一样。