公开(公告)号：US5508554A

公开(公告)日：1996-04-16

申请号：US294504

申请日：1994-08-23

申请人： Shinichiro Takatani ,  Takeshi Kikawa ,  Yoko Uchida

发明人： Shinichiro Takatani ,  Takeshi Kikawa ,  Yoko Uchida

IPC分类号： H01L21/02 ,  H01L21/20 ,  H01L27/00 ,  H01L29/205 ,  H01L29/267 ,  H01L29/32 ,  H01L29/30 ,  H01L31/0328 ,  H01L31/0336

CPC分类号： H01L29/32 ,  H01L21/02381 ,  H01L21/02395 ,  H01L21/02439 ,  H01L21/02463 ,  H01L21/02502 ,  H01L21/02507 ,  H01L21/02546 ,  H01L29/205 ,  H01L29/267

摘要： Disclosed is a semiconductor device capable of suppressing the generation of dislocations due to the difference in lattice constant by insertion of one or more defect type compound layers in a semiconductor layered structure. The strain generated by the mismatch of the lattice is relaxed by a large amount of vacancies contained in the defect type compound layer, to suppress the generation and the propagation of dislocations, thus inexpensively fabricating a semiconductor device with less deterioration of the characteristics due to defects with good repeatability.

摘要翻译： 公开了一种半导体器件，其能够通过在半导体层叠结构中插入一个或多个缺陷型化合物层来抑制由于晶格常数的差异而产生的位错。 由缺陷型化合物层中含有的大量空位而使晶格失配产生的应变被抑制，以抑制位错的产生和扩散，从而廉价地制造由于缺陷导致的特性劣化较少的半导体器件 具有良好的重复性。

公开(公告)号：US5399230A

公开(公告)日：1995-03-21

申请号：US72407

申请日：1993-06-07

申请人： Shinichiro Takatani ,  Takeshi Kikawa ,  Chushirou Kusano ,  Masatoshi Nakazawa

发明人： Shinichiro Takatani ,  Takeshi Kikawa ,  Chushirou Kusano ,  Masatoshi Nakazawa

IPC分类号： C23F4/00 ,  H01L21/285 ,  H01L21/302 ,  H01L21/304 ,  H01L21/306 ,  H01L21/331 ,  H01L21/335 ,  H01L23/14 ,  B44C1/22

CPC分类号： H01L29/66318 ,  H01L21/28587 ,  H01L21/30617 ,  H01L29/66462

摘要： A compound semiconductor is etched by a step of substituting a composite element of a compound semiconductor with other element, thereby forming a compound layer on the surface of the compound semiconductor and a step of removing the compound layer from the surface. Etching depth is controlled not by etching time, but by the number of runs (repetitions) of the etching step, and thus can be precisely controlled.

摘要翻译： 通过用化合物半导体的复合元件代替其它元件的步骤来蚀刻化合物半导体，从而在化合物半导体的表面上形成化合物层，以及从表面除去化合物层的步骤。 蚀刻深度不受蚀刻时间控制，而是通过蚀刻步骤的次数（重复）来控制，因此可以精确地控制。

公开(公告)号：US20090026499A1

公开(公告)日：2009-01-29

申请号：US12019137

申请日：2008-01-24

申请人： Takeshi Kikawa ,  Shinichiro Takatani ,  Tomihisa Yukimoto ,  Yohei Otoki ,  Hiroyuki Kamogawa ,  Tomoyoshi Mishima

发明人： Takeshi Kikawa ,  Shinichiro Takatani ,  Tomihisa Yukimoto ,  Yohei Otoki ,  Hiroyuki Kamogawa ,  Tomoyoshi Mishima

IPC分类号： H01L29/78

CPC分类号： H01L29/7783 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/02389 ,  H01L21/02392 ,  H01L21/02395 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/02461 ,  H01L21/02463 ,  H01L27/0605 ,  H01L29/155 ,  H01L29/20 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/8605

摘要： A semiconductor integrated circuit device having a plurality of semiconductor electronic members including a field effect transistor, intended for suppressing a sidegating effect on the field effect transistor, wherein accumulation of majority carriers of the field effect transistor is suppressed at the interface of heterojunction in the buffering compound semiconductor layer and the interface between the substrate and the buffering compound semiconductor layer in the device isolation region so that the discontinuity of energy forbidden bands of the semiconductors caused at the interfaces does not form a potential barrier upon conduction of the carriers into the substrate, whereby the sidegating effect from the resistor element, etc. placed adjacently to the field effect transistor can be decreased drastically.

摘要翻译： 一种半导体集成电路器件，具有多个包括场效应晶体管的半导体电子元件，旨在抑制场效应晶体管的侧向效应，其中场效应晶体管的多数载流子的积累被抑制在缓冲中的异质结界面处 化合物半导体层以及衬底和器件隔离区中的缓冲化合物半导体层之间的界面，使得在界面处引起的半导体的能量禁带的不连续性在载体传导到衬底中时不形成势垒， 从而可以显着降低来自与场效应晶体管相邻放置的电阻元件等的侧向起作用。

公开(公告)号：US20170194474A1

公开(公告)日：2017-07-06

申请号：US15390590

申请日：2016-12-26

申请人： Riichiro Shirota ,  Shinichiro Takatani

发明人： Riichiro Shirota ,  Shinichiro Takatani

IPC分类号： H01L29/778 ,  H01L29/205 ,  H01L29/788 ,  H01L29/423 ,  H01L29/06 ,  H01L29/51 ,  H01L29/792 ,  H01L29/20 ,  H01L29/417

CPC分类号： H01L29/7787 ,  H01L28/00 ,  H01L29/0642 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/402 ,  H01L29/41758 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/517 ,  H01L29/7786 ,  H01L29/7831 ,  H01L29/7832 ,  H01L29/788 ,  H01L29/792

摘要： A nitride semiconductor transistor device is disclosed to provide a normally-off nitride semiconductor transistor device which is excellent in switching properties with less dispersion of the properties. The nitride semiconductor transistor device has a buffer layer, a GaN layer, and an AlGaN layer in turn grown on a substrate. A first insulating film, a charge storage layer, a second insulating film, and a control electrode are in turn grown on the AlGaN layer. A source electrode and a drain electrode are formed to sandwich the charge storage layer over the AlGaN layer. A threshold voltage to shut off an electric current flowing between the source and drain electrodes through a conductive channel induced at an interface of the AlGaN layer and the GaN layer is made positive by adjusting charge stored in the charge storage layer.

公开(公告)号：US20110156983A1

公开(公告)日：2011-06-30

申请号：US12929940

申请日：2011-02-25

申请人： Takashi Ogawa ,  Shinichiro Takatani ,  Shigeki Koya ,  Hiroyuki Takazawa ,  Shinya Osakabe ,  Akishige Nakajima ,  Yasushi Shigeno

发明人： Takashi Ogawa ,  Shinichiro Takatani ,  Shigeki Koya ,  Hiroyuki Takazawa ,  Shinya Osakabe ,  Akishige Nakajima ,  Yasushi Shigeno

IPC分类号： H01Q1/50 ,  H01L29/12

CPC分类号： H01L27/0605 ,  H01L27/0629 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/7783 ,  H01L2924/0002 ,  H01L2924/00

摘要： A switching element is provided that realizes an stabilize a potential between the gates of the multi-gates without an increase in the insertion loss, and an antenna switch circuit and a radio frequency module each using the switch element. The switching element includes two ohmic electrodes 39, 40 formed on a semiconductor substrate, at least two gate electrodes 41, 42 disposed between the two ohmic electrodes, and a conductive region 45 disposed between the adjacent gate electrodes among the at least two gate electrodes, a field effective transistor being structured by the two ohmic electrodes, the at least two gate electrodes, and the conductive region. The conductive region has a wider portion that is wider in width than the conductive region interposed between the adjacent gate electrodes on one end thereof. The distance between the adjacent gate electrodes is narrower than the width of the wider portion. Resistors 44, 46 are connected in series between the two ohmic electrodes through the wider portion.

公开(公告)号：US07899412B2

公开(公告)日：2011-03-01

申请号：US12805409

申请日：2010-07-29

申请人： Takashi Ogawa ,  Shinichiro Takatani ,  Shigeki Koya ,  Hiroyuki Takazawa ,  Shinya Osakabe ,  Akishige Nakajima ,  Yasushi Shigeno

发明人： Takashi Ogawa ,  Shinichiro Takatani ,  Shigeki Koya ,  Hiroyuki Takazawa ,  Shinya Osakabe ,  Akishige Nakajima ,  Yasushi Shigeno

IPC分类号： H04B1/44

CPC分类号： H01L27/0605 ,  H01L27/0629 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/7783 ,  H01L2924/0002 ,  H01L2924/00

摘要： A switching element is provided that realizes an stabilize a potential between the gates of the multi-gates without an increase in the insertion loss, and an antenna switch circuit and a radio frequency module each using the switch element. The switching element includes two ohmic electrodes 39, 40 formed on a semiconductor substrate, at least two gate electrodes 41, 42 disposed between the two ohmic electrodes, and a conductive region 45 disposed between the adjacent gate electrodes among the at least two gate electrodes, a field effective transistor being structured by the two ohmic electrodes, the at least two gate electrodes, and the conductive region. The conductive region has a wider portion that is wider in width than the conductive region interposed between the adjacent gate electrodes on one end thereof. The distance between the adjacent gate electrodes is narrower than the width of the wider portion. Resistors 44, 46 are connected in series between the two ohmic electrodes through the wider portion.

摘要翻译： 提供了一种开关元件，其实现了在不增加插入损耗的情况下使多栅极的栅极之间的电位稳定，并且每个使用开关元件的天线开关电路和射频模块。 开关元件包括形成在半导体衬底上的两个欧姆电极39,40，设置在两个欧姆电极之间的至少两个栅极电极41,42以及设置在至少两个栅电极之间的相邻栅电极之间的导电区域45， 场效应晶体管由两个欧姆电极，至少两个栅极电极和导电区域构成。 导电区域的宽度部分的宽度比插入在其一端的相邻栅电极之间的导电区域宽。 相邻栅电极之间的距离比较宽部分的宽度窄。 电阻器44,46通过较宽部分串联连接在两个欧姆电极之间。

公开(公告)号：US20100297960A1

公开(公告)日：2010-11-25

申请号：US12805409

申请日：2010-07-29

申请人： Takashi Ogawa ,  Shinichiro Takatani ,  Shigeki Koya ,  Hiroyuki Takazawa ,  Shinya Osakabe ,  Akishige Nakajima ,  Yasushi Shigeno

发明人： Takashi Ogawa ,  Shinichiro Takatani ,  Shigeki Koya ,  Hiroyuki Takazawa ,  Shinya Osakabe ,  Akishige Nakajima ,  Yasushi Shigeno

IPC分类号： H04B1/44 ,  H01L29/778

CPC分类号： H01L27/0605 ,  H01L27/0629 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/7783 ,  H01L2924/0002 ,  H01L2924/00

摘要： A switching element is provided that realizes an stabilize a potential between the gates of the multi-gates without an increase in the insertion loss, and an antenna switch circuit and a radio frequency module each using the switch element. The switching element includes two ohmic electrodes 39, 40 formed on a semiconductor substrate, at least two gate electrodes 41, 42 disposed between the two ohmic electrodes, and a conductive region 45 disposed between the adjacent gate electrodes among the at least two gate electrodes, a field effective transistor being structured by the two ohmic electrodes, the at least two gate electrodes, and the conductive region. The conductive region has a wider portion that is wider in width than the conductive region interposed between the adjacent gate electrodes on one end thereof. The distance between the adjacent gate electrodes is narrower than the width of the wider portion. Resistors 44, 46 are connected in series between the two ohmic electrodes through the wider portion.

公开(公告)号：US07256437B2

公开(公告)日：2007-08-14

申请号：US10920344

申请日：2004-08-18

申请人： Hiroshi Miki ,  Keiko Kushida ,  Yasuhiro Shimamoto ,  Shinichiro Takatani ,  Yoshihisa Fujisaki ,  Hiromi Nakai

发明人： Hiroshi Miki ,  Keiko Kushida ,  Yasuhiro Shimamoto ,  Shinichiro Takatani ,  Yoshihisa Fujisaki ,  Hiromi Nakai

IPC分类号： H01L29/76

CPC分类号： H01L28/75 ,  H01L28/55 ,  H01L28/57 ,  H01L28/60

摘要： The upper electrode of a capacitor is constituted of laminated films which act to prevent hydrogen atoms from reaching the capacitor electrodes and degrading performance. In one example, a four layer upper electrode respectively acts as a Schottky barrier layer, a hydrogen diffusion preventing layer, a reaction preventing layer, and an adsorption inhibiting layer. Therefore, the occurrence of a capacitance drop, imperfect insulation, and electrode peeling in the semiconductor device due to a reducing atmosphere can be prevented. In addition, the long-term reliability of the device can be improved.

摘要翻译： 电容器的上电极由层叠膜构成，其用于防止氢原子到达电容器电极并降低性能。 在一个示例中，四层上电极分别用作肖特基势垒层，氢扩散防止层，反应防止层和吸附抑制层。 因此，可以防止由于还原气氛导致半导体器件中的电容下降，绝缘不良和电极剥离的发生。 另外，可以提高装置的长期可靠性。

公开(公告)号：US11489050B2

公开(公告)日：2022-11-01

申请号：US17143144

申请日：2021-01-06

申请人： Shinichiro Takatani ,  Riichiro Shirota

发明人： Shinichiro Takatani ,  Riichiro Shirota

IPC分类号： H01L29/40 ,  H01L29/778 ,  H01L29/06 ,  H01L29/423 ,  H01L29/51 ,  H01L29/205 ,  H01L29/20

摘要： A normally-off vertical nitride semiconductor transistor device with low threshold voltage variation includes a drift layer containing a nitride semiconductor, a channel region electrically connected to the drift layer, a source electrode, a drain electrode, a gate insulating film, and a gate electrode. The gate insulating film includes at least a first insulating film located at the channel region side, a second insulating film located at the gate electrode side, and a third insulating film between the second insulating film and the gate electrode, wherein the second insulating film has charge traps with energy levels located inside the band gaps of both the first and third insulating films, and the threshold voltage is adjusted by charges accumulated in the charge traps. The threshold voltage is used to block flowing current by substantially eliminating conduction carriers of the channel region by voltage applied to the gate electrode.

公开(公告)号：US11201233B2

公开(公告)日：2021-12-14

申请号：US16931398

申请日：2020-07-16

申请人： Shinichiro Takatani

发明人： Shinichiro Takatani

IPC分类号： H01L29/737 ,  H01L29/10 ,  H01L29/08 ,  H01L29/205

摘要： The invention provides a structure of an emitter layer and a base layer that reduces the influence of a conduction band energy barrier generated at an interface between the emitter layer and the base layer on power amplifier characteristics for a GaAs HBT using InGaAs grown by pseudomorphic growth in the base layer. In the first invention, InGaP having a CuPt-type ordering is used in the emitter layer. In the second invention, a p-type impurity concentration of an InGaAs base layer grown by pseudomorphic growth is less in an emitter layer side portion than in a collector layer side portion.