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    BOND PAD FOR SEMICONDUCTOR DIE
    3.
    发明申请
    BOND PAD FOR SEMICONDUCTOR DIE 有权

    公开(公告)号：US20120049389A1

    公开(公告)日：2012-03-01

    申请号：US12874204

    申请日：2010-09-01

    Applicant: Chetan Verma ,  Shailesh Kumar ,  Meng Kong Lye

    Inventor： Chetan Verma ,  Shailesh Kumar ,  Meng Kong Lye

    IPC: H01L23/488

    CPC classification number: H01L24/06 ,  H01L22/32 ,  H01L24/05 ,  H01L2224/04042 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00

    Abstract: A semiconductor die has rows of bond pads along the edges of a major surface. The corners of the die are designated as keep out areas, with design layout rules prohibiting a probe-able bond pad from being placed in the keep out areas so that a minimum distance may be maintained between distal ends of adjacent rows of bond pads (i.e., bond pads along adjacent edges). The bond pads of each row have IO pad areas that are aligned with each other and IO probe areas that are aligned with each other. A generally L-shaped bond pad includes a first, vertical part that extends inwardly from an edge of the semiconductor die and a second, horizontal part connected to the vertical part. The L-shaped bond pad may be placed between a last bond pad in a row and a corner keep out area, and the second part of the L-shaped bond pad extends into the corner keep out area. The first part has an IO pad area that is in alignment with the IO pad areas of the other bond pads in the same row, and the second part has an IO probe area that is in alignment with the IO probe areas of the bond pads in the adjacent row. The L-shaped bond pad does not violate design rules even though a part of the pad extends into the corner keep out area.

    Abstract translation: 半导体管芯沿着主表面的边缘具有一排接合焊盘。 模具的角被指定为保留区域，其设计布局规则禁止可探测的焊盘放置在保留区域中，使得可以在相邻排的焊盘的末端之间保持最小距离（即 ，沿着相邻边缘的接合垫）。 每行的接合焊盘具有彼此对准的IO焊盘区域和彼此对准的IO探针区域。 大致L形接合焊盘包括从半导体管芯的边缘向内延伸的第一垂直部分和连接到垂直部分的第二水平部分。 L形接合焊盘可以放置在一行中的最后接合焊盘和拐角保持区域之间，并且L形接合焊盘的第二部分延伸到角落保持区域中。 第一部分具有与同一行中的其它接合焊盘的IO焊盘区域对准的IO焊盘区域，并且第二部分具有与焊盘的IO探针区域对准的IO探针区域 相邻行。 即使垫的一部分延伸到角落保持区域，L形接合垫也不违反设计规则。

    Bond pad for semiconductor die
    4.
    发明授权
    Bond pad for semiconductor die 有权
    用于半导体管芯的焊盘

    公开(公告)号：US08242613B2

    公开(公告)日：2012-08-14

    申请号：US12874204

    申请日：2010-09-01

    Applicant: Chetan Verma ,  Shailesh Kumar ,  Meng Kong Lye

    Inventor： Chetan Verma ,  Shailesh Kumar ,  Meng Kong Lye

    IPC: H01L23/488 ,  H01L23/485 ,  H01L21/768 ,  H01L23/48

    CPC classification number: H01L24/06 ,  H01L22/32 ,  H01L24/05 ,  H01L2224/04042 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00

    Abstract: A semiconductor die has rows of bond pads along the edges of a major surface. The corners of the die are designated as keep out areas, with design layout rules prohibiting a probe-able bond pad from being placed in the keep out areas so that a minimum distance may be maintained between distal ends of adjacent rows of bond pads (i.e., bond pads along adjacent edges). The bond pads of each row have IO pad areas that are aligned with each other and IO probe areas that are aligned with each other. A generally L-shaped bond pad includes a first, vertical part that extends inwardly from an edge of the semiconductor die and a second, horizontal part connected to the vertical part. The L-shaped bond pad may be placed between a last bond pad in a row and a corner keep out area, and the second part of the L-shaped bond pad extends into the corner keep out area. The first part has an IO pad area that is in alignment with the IO pad areas of the other bond pads in the same row, and the second part has an IO probe area that is in alignment with the IO probe areas of the bond pads in the adjacent row. The L-shaped bond pad does not violate design rules even though a part of the pad extends into the corner keep out area.

    Abstract translation: 半导体管芯沿着主表面的边缘具有一排接合焊盘。 模具的角被指定为保留区域，其设计布局规则禁止可探测的焊盘放置在保留区域中，使得可以在相邻排的焊盘的末端之间保持最小距离（即 ，沿着相邻边缘的接合垫）。 每行的接合焊盘具有彼此对准的IO焊盘区域和彼此对准的IO探针区域。 大致L形接合焊盘包括从半导体管芯的边缘向内延伸的第一垂直部分和连接到垂直部分的第二水平部分。 L形接合焊盘可以放置在一行中的最后接合焊盘和拐角保持区域之间，并且L形接合焊盘的第二部分延伸到角落保持区域中。 第一部分具有与同一行中的其它接合焊盘的IO焊盘区域对准的IO焊盘区域，并且第二部分具有与焊盘的IO探针区域对准的IO探针区域 相邻行。 即使垫的一部分延伸到角落保持区域，L形接合垫也不违反设计规则。

    LEAD FRAME AND SEMICONDUCTOR PACKAGE MANUFACTURED THEREWITH
    5.
    发明申请
    LEAD FRAME AND SEMICONDUCTOR PACKAGE MANUFACTURED THEREWITH 审中-公开
    引导框架和制造的半导体封装

    公开(公告)号：US20110204498A1

    公开(公告)日：2011-08-25

    申请号：US12712159

    申请日：2010-02-24

    Applicant: Yin Kheng Au ,  Mohd Rusli Ibrahim ,  Meng Kong Lye ,  Zi Song Poh ,  Seng Kiong Teng ,  Kesyakumar V.C. Muniandy

    Inventor： Yin Kheng Au ,  Mohd Rusli Ibrahim ,  Meng Kong Lye ,  Zi Song Poh ,  Seng Kiong Teng ,  Kesyakumar V.C. Muniandy

    IPC: H01L23/495

    CPC classification number: H01L23/49541 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

    Abstract: A lead frame for a semiconductor package has a flag to which a semiconductor die is mounted. Tie bars are coupled to the flag. There is a first set of leads and each first set lead in the first set of leads has a first set lead parallel length and a first set lead tapered length. The first set lead parallel length of each first set lead has a constant width and edges that are parallel to edges of all other first set lead parallel lengths. A free end region of the first set lead tapered length of each first set lead provides a first set lead bond target region. There is a second set of leads disposed between a first one of the tie bars and the first set of leads. Each second set lead, in the second set of leads, has a second set lead parallel length and a second set lead tapered length. The second set lead parallel length of each second set lead has a constant width and edges that are parallel to edges of all other second set lead parallel lengths in the second set of leads and also parallel to the edges of first set lead parallel lengths. At least one second set lead has an extension length extending inwardly from the second set lead tapered length, the extension length has a constant width and provides a second set lead bond target region. Wire bond leads electrically couple both the first set lead bond target region and second set lead bond target region to respective die external electrical connection pads on a surface of the die and a package body encloses the die.

    Abstract translation: 半导体封装的引线框架具有安装有半导体管芯的标志。 领带条与标志相连。 存在第一组引线，并且第一组引线中的每个第一组引线具有第一组引线平行长度和第一组引线锥形长度。 每个第一组引线的第一组引线平行长度具有恒定的宽度，并且与所有其它第一组引线平行长度的边缘平行的边缘。 每个第一集合引线的第一组引线锥形长度的自由端区域提供第一组引线键合目标区域。 存在设置在第一组连杆和第一组引线之间的第二组引线。 在第二组引线中的每个第二设定引线具有第二设定引线平行长度和第二设定引线锥形长度。 每个第二组引线的第二组引线平行长度具有恒定的宽度，并且边缘平行于第二组引线中的所有其它第二设定引线平行长度的边缘，并且平行于第一组引线平行长度的边缘。 至少一个第二固定引线具有从第二组引线锥形长度向内延伸的延伸长度，延伸长度具有恒定的宽度并且提供第二组引线键合目标区域。 引线接合引线将第一组引线接合目标区域和第二组引线接合目标区域电耦合到管芯表面上的相应管芯外部电连接焊盘，并且封装主体封装管芯。

    Semiconductor package with stress relief and heat spreader
    6.
    发明授权
    Semiconductor package with stress relief and heat spreader 有权
    具有应力消除和散热器的半导体封装

    公开(公告)号：US09196576B2

    公开(公告)日：2015-11-24

    申请号：US14277801

    申请日：2014-05-15

    Applicant: Kai Yun Yow ,  Poh Leng Eu ,  Meng Kong Lye ,  You Ge ,  Penglin Mei

    Inventor： Kai Yun Yow ,  Poh Leng Eu ,  Meng Kong Lye ,  You Ge ,  Penglin Mei

    IPC: H01L23/495 ,  H01L23/34

    CPC classification number: H01L23/49568 ,  H01L23/49503 ,  H01L23/49551 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48471 ,  H01L2924/00014 ,  H01L2224/4554

    Abstract: A semiconductor device has a die mounted on a die paddle that is elevated above and thermally connected via tie bars to a heat sink structure. Heat generated by the die flows from the die to the die paddle to the tie bars to the heat sink structure and then to either the external environment or to an external heat sink. By elevating the die/paddle sub-assembly above the heat sink structure, the packaged device is less susceptible to delamination between the die and die attach adhesive and/or the die attach adhesive and the die paddle. An optional heat sink ring can surround the die paddle.

    Abstract translation: 半导体器件具有安装在芯片上的管芯，其上升并且经由连接杆热连接到散热器结构。 由模具产生的热量从模具流到模具板到连接杆到散热器结构，然后流到外部环境或外部散热器。 通过将模具/桨叶子组件提升到散热器结构上方，封装的装置不易受到管芯和管芯附接粘合剂和/或管芯附接粘合剂和管芯焊盘之间的分层的影响。 可选的散热片环可围绕裸片。

    Method for reducing surface area of pad limited semiconductor die layout
    8.
    发明授权
    Method for reducing surface area of pad limited semiconductor die layout 有权
    减少焊盘限制半导体管芯布局的表面积的方法

    公开(公告)号：US08291368B2

    公开(公告)日：2012-10-16

    申请号：US13020814

    申请日：2011-02-04

    Applicant: Chetan Verma ,  Sumeet Aggarwal ,  Meng Kong Lye

    Inventor： Chetan Verma ,  Sumeet Aggarwal ,  Meng Kong Lye

    IPC: G06F17/50

    CPC classification number: G06F17/5072 ,  G06F2217/40 ,  H01L24/06 ,  H01L2224/05553 ,  H01L2224/49113

    Abstract: A method for reducing a surface area of a pad limited semiconductor die layout includes choosing an outer die pad row from a group of outer die pad rows on the semiconductor die, each of the outer die pad rows being adjacent an edge of the semiconductor die. Next, the method performs selecting, from the outer die pad row, a common die pad group with die pads that are arranged to be electrically connected to an external connection pad. The method then performs repositioning a subgroup of the common die pad group on an inner die pad row, the inner pad row being adjacent the outer die pad row. After he repositioning there is performed a step of adjusting positions of at least some of the remaining pads in the outer die pad row thereby reducing an overall length of the outer die pad row. The method then provides for repeating the above steps until the surface area of a pad limited semiconductor die cannot be reduced any further by the step of adjusting positions or until every common die pad group, on every one of the outer die pad rows, has been selected by the selecting step.

    Abstract translation: 一种用于减小焊盘限制半导体管芯布局的表面积的方法包括从半导体管芯上的一组外管芯焊盘行中选择外管芯焊盘行，每个外管芯焊盘排与半导体管芯的边缘相邻。 接下来，该方法执行从外管芯焊盘行中选择配置为电连接到外部连接焊盘的管芯焊盘的公共管芯焊盘组。 然后，该方法执行将内部焊盘排上的公共管芯焊盘组的子组重新定位，内部焊盘排与外部管芯焊盘排相邻。 在重新定位之后，执行调整外部管芯焊盘列中的至少一些剩余焊盘的位置的步骤，从而减小外部管芯焊盘排的总长度。 该方法然后提供重复上述步骤，直到通过调整位置的步骤不再进一步减小衬垫限制半导体管芯的表面积，或者直到在每个外管芯焊盘排上的每个公共管芯焊盘组已被 通过选择步骤选择。

    Lead frame based semiconductor device with routing substrate
    9.
    发明授权
    Lead frame based semiconductor device with routing substrate 有权
    引线框架半导体器件与布线衬底

    公开(公告)号：US08980690B1

    公开(公告)日：2015-03-17

    申请号：US14462565

    申请日：2014-08-19

    Applicant: Penglin Mei ,  You Ge ,  Meng Kong Lye

    Inventor： Penglin Mei ,  You Ge ,  Meng Kong Lye

    IPC: H01L21/44 ,  H01L23/495

    CPC classification number: H01L23/49541 ,  H01L21/568 ,  H01L23/49531 ,  H01L24/48 ,  H01L2224/05554 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/48145 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/0665

    Abstract: A semiconductor device including a lead frame, a routing substrate disposed within the lead frame, and an active component mounted on the routing substrate. The active component has a plurality of die pads. The routing substrate includes a set of first bond pads, a set of second bond pads, and interconnections, where each interconnection provides an electrical connection between a first bond pad and a corresponding second bond pad. The semiconductor device further includes electrical couplings between one or more of die pads of the active component and corresponding first bond pads of the routing substrate, as well as electrical couplings between leads of the lead frame and respective second bond pads of the routing substrate.

    Abstract translation: 一种半导体器件，包括引线框架，布置在引线框架内的布线基板以及安装在布线基板上的有源部件。 有源部件具有多个管芯焊盘。 路由衬底包括一组第一接合焊盘，一组第二接合焊盘和互连，其中每个互连提供第一接合焊盘和相应的第二接合焊盘之间的电连接。 该半导体器件还包括在有源部件的一个或多个管芯焊盘和布线衬底的对应的第一焊盘之间的电耦合，以及引线框架的引线与布线衬底的相应的第二接合焊盘之间的电耦合。

    Common pin for multi-die semiconductor package
    10.
    发明授权
    Common pin for multi-die semiconductor package 有权
    多芯片半导体封装的通用引脚

    公开(公告)号：US09196578B1

    公开(公告)日：2015-11-24

    申请号：US14459337

    申请日：2014-08-14

    Applicant: Sheau Mei Lim ,  Meng Kong Lye ,  Pei Fan Tong

    Inventor： Sheau Mei Lim ,  Meng Kong Lye ,  Pei Fan Tong

    IPC: H01L23/495

    CPC classification number: H01L23/49575 ,  H01L23/49503 ,  H01L23/49541 ,  H01L2224/05554 ,  H01L2224/49113 ,  H01L2224/49171

    Abstract: A semiconductor package has multiple dies and an interior power bar that extends within an interior space formed within the die flag between the dies. The bond pads located on the interior side of each die are wire-bonded to the interior power bar. Some embodiments may have more than two dies and/or more than one interior power bar between each pair of adjacent dies.

    Abstract translation: 半导体封装具有多个管芯和内部电源杆，其在形成在管芯之间的管芯标记内的内部空间内延伸。 位于每个模具的内侧的接合焊盘被引线接合到内部电源杆。 一些实施例可以在每对相邻的模具之间具有多于两个的模具和/或多于一个的内部功率杆。

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