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    Method for reducing surface area of pad limited semiconductor die layout
    1.
    发明授权
    Method for reducing surface area of pad limited semiconductor die layout 有权
    减少焊盘限制半导体管芯布局的表面积的方法

    公开(公告)号：US08291368B2

    公开(公告)日：2012-10-16

    申请号：US13020814

    申请日：2011-02-04

    申请人： Chetan Verma ,  Sumeet Aggarwal ,  Meng Kong Lye

    发明人： Chetan Verma ,  Sumeet Aggarwal ,  Meng Kong Lye

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5072 ,  G06F2217/40 ,  H01L24/06 ,  H01L2224/05553 ,  H01L2224/49113

    摘要： A method for reducing a surface area of a pad limited semiconductor die layout includes choosing an outer die pad row from a group of outer die pad rows on the semiconductor die, each of the outer die pad rows being adjacent an edge of the semiconductor die. Next, the method performs selecting, from the outer die pad row, a common die pad group with die pads that are arranged to be electrically connected to an external connection pad. The method then performs repositioning a subgroup of the common die pad group on an inner die pad row, the inner pad row being adjacent the outer die pad row. After he repositioning there is performed a step of adjusting positions of at least some of the remaining pads in the outer die pad row thereby reducing an overall length of the outer die pad row. The method then provides for repeating the above steps until the surface area of a pad limited semiconductor die cannot be reduced any further by the step of adjusting positions or until every common die pad group, on every one of the outer die pad rows, has been selected by the selecting step.

    摘要翻译： 一种用于减小焊盘限制半导体管芯布局的表面积的方法包括从半导体管芯上的一组外管芯焊盘行中选择外管芯焊盘行，每个外管芯焊盘排与半导体管芯的边缘相邻。 接下来，该方法执行从外管芯焊盘行中选择配置为电连接到外部连接焊盘的管芯焊盘的公共管芯焊盘组。 然后，该方法执行将内部焊盘排上的公共管芯焊盘组的子组重新定位，内部焊盘排与外部管芯焊盘排相邻。 在重新定位之后，执行调整外部管芯焊盘列中的至少一些剩余焊盘的位置的步骤，从而减小外部管芯焊盘排的总长度。 该方法然后提供重复上述步骤，直到通过调整位置的步骤不再进一步减小衬垫限制半导体管芯的表面积，或者直到在每个外管芯焊盘排上的每个公共管芯焊盘组已被 通过选择步骤选择。

    BOND PAD FOR SEMICONDUCTOR DIE
    2.
    发明申请
    BOND PAD FOR SEMICONDUCTOR DIE 有权

    公开(公告)号：US20120049389A1

    公开(公告)日：2012-03-01

    申请号：US12874204

    申请日：2010-09-01

    申请人： Chetan Verma ,  Shailesh Kumar ,  Meng Kong Lye

    发明人： Chetan Verma ,  Shailesh Kumar ,  Meng Kong Lye

    IPC分类号： H01L23/488

    CPC分类号： H01L24/06 ,  H01L22/32 ,  H01L24/05 ,  H01L2224/04042 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00

    摘要： A semiconductor die has rows of bond pads along the edges of a major surface. The corners of the die are designated as keep out areas, with design layout rules prohibiting a probe-able bond pad from being placed in the keep out areas so that a minimum distance may be maintained between distal ends of adjacent rows of bond pads (i.e., bond pads along adjacent edges). The bond pads of each row have IO pad areas that are aligned with each other and IO probe areas that are aligned with each other. A generally L-shaped bond pad includes a first, vertical part that extends inwardly from an edge of the semiconductor die and a second, horizontal part connected to the vertical part. The L-shaped bond pad may be placed between a last bond pad in a row and a corner keep out area, and the second part of the L-shaped bond pad extends into the corner keep out area. The first part has an IO pad area that is in alignment with the IO pad areas of the other bond pads in the same row, and the second part has an IO probe area that is in alignment with the IO probe areas of the bond pads in the adjacent row. The L-shaped bond pad does not violate design rules even though a part of the pad extends into the corner keep out area.

    摘要翻译： 半导体管芯沿着主表面的边缘具有一排接合焊盘。 模具的角被指定为保留区域，其设计布局规则禁止可探测的焊盘放置在保留区域中，使得可以在相邻排的焊盘的末端之间保持最小距离（即 ，沿着相邻边缘的接合垫）。 每行的接合焊盘具有彼此对准的IO焊盘区域和彼此对准的IO探针区域。 大致L形接合焊盘包括从半导体管芯的边缘向内延伸的第一垂直部分和连接到垂直部分的第二水平部分。 L形接合焊盘可以放置在一行中的最后接合焊盘和拐角保持区域之间，并且L形接合焊盘的第二部分延伸到角落保持区域中。 第一部分具有与同一行中的其它接合焊盘的IO焊盘区域对准的IO焊盘区域，并且第二部分具有与焊盘的IO探针区域对准的IO探针区域 相邻行。 即使垫的一部分延伸到角落保持区域，L形接合垫也不违反设计规则。

    Bond pad for semiconductor die
    3.
    发明授权
    Bond pad for semiconductor die 有权
    用于半导体管芯的焊盘

    公开(公告)号：US08242613B2

    公开(公告)日：2012-08-14

    申请号：US12874204

    申请日：2010-09-01

    申请人： Chetan Verma ,  Shailesh Kumar ,  Meng Kong Lye

    发明人： Chetan Verma ,  Shailesh Kumar ,  Meng Kong Lye

    IPC分类号： H01L23/488 ,  H01L23/485 ,  H01L21/768 ,  H01L23/48

    CPC分类号： H01L24/06 ,  H01L22/32 ,  H01L24/05 ,  H01L2224/04042 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00

    摘要： A semiconductor die has rows of bond pads along the edges of a major surface. The corners of the die are designated as keep out areas, with design layout rules prohibiting a probe-able bond pad from being placed in the keep out areas so that a minimum distance may be maintained between distal ends of adjacent rows of bond pads (i.e., bond pads along adjacent edges). The bond pads of each row have IO pad areas that are aligned with each other and IO probe areas that are aligned with each other. A generally L-shaped bond pad includes a first, vertical part that extends inwardly from an edge of the semiconductor die and a second, horizontal part connected to the vertical part. The L-shaped bond pad may be placed between a last bond pad in a row and a corner keep out area, and the second part of the L-shaped bond pad extends into the corner keep out area. The first part has an IO pad area that is in alignment with the IO pad areas of the other bond pads in the same row, and the second part has an IO probe area that is in alignment with the IO probe areas of the bond pads in the adjacent row. The L-shaped bond pad does not violate design rules even though a part of the pad extends into the corner keep out area.

    摘要翻译： 半导体管芯沿着主表面的边缘具有一排接合焊盘。 模具的角被指定为保留区域，其设计布局规则禁止可探测的焊盘放置在保留区域中，使得可以在相邻排的焊盘的末端之间保持最小距离（即 ，沿着相邻边缘的接合垫）。 每行的接合焊盘具有彼此对准的IO焊盘区域和彼此对准的IO探针区域。 大致L形接合焊盘包括从半导体管芯的边缘向内延伸的第一垂直部分和连接到垂直部分的第二水平部分。 L形接合焊盘可以放置在一行中的最后接合焊盘和拐角保持区域之间，并且L形接合焊盘的第二部分延伸到角落保持区域中。 第一部分具有与同一行中的其它接合焊盘的IO焊盘区域对准的IO焊盘区域，并且第二部分具有与焊盘的IO探针区域对准的IO探针区域 相邻行。 即使垫的一部分延伸到角落保持区域，L形接合垫也不违反设计规则。

    DUAL-EDGE GATED CLOCK SIGNAL GENERATOR
    5.
    发明申请
    DUAL-EDGE GATED CLOCK SIGNAL GENERATOR 有权
    双边门控时钟信号发生器

    公开(公告)号：US20150316950A1

    公开(公告)日：2015-11-05

    申请号：US14267933

    申请日：2014-05-02

    申请人： Amit Kumar Dey ,  Himanshu Mangal ,  Kulbhushan Misri ,  Amit Roy ,  Vijay Tayal ,  Chetan Verma

    发明人： Amit Kumar Dey ,  Himanshu Mangal ,  Kulbhushan Misri ,  Amit Roy ,  Vijay Tayal ,  Chetan Verma

    IPC分类号： G06F1/04 ,  H03K19/20

    CPC分类号： G06F1/04 ,  H03K19/096 ,  H03K19/20

    摘要： A clock signal generator provides a gated clock signal GCLK to trigger operation of dual-edge triggered circuits. A first detector generates, while a clock gating signal /EN is asserted, a first detector output signal that is asserted or de-asserted as a function of disjunction or conjunction respectively of the values that an input clock signal CLK and the gated clock signal GCLK had when the clock gating signal /EN transitioned. A second detector generates, while the clock gating signal /EN is de-asserted, as the value of the gated clock signal GCLK, the value CLK or its complement /CLK as a function of the first detector output signal. When the clock gating signal /EN is asserted, the second detector maintains the value that the gated clock signal GCLK had when the clock gating signal /EN transitioned from de-asserted to asserted.

    摘要翻译： 时钟信号发生器提供门控时钟信号GCLK以触发双边缘触发电路的操作。 当时钟门控信号/ EN被断言时，第一检测器产生一个第一检测器输出信号，该第一检测器输出信号被断言或取消断言作为分离或分别与输入时钟信号CLK和门控时钟信号GCLK 当时钟门控信号/ EN转换。 当门控时钟信号/ EN被取消置位时，第二个检测器产生门控时钟信号GCLK的值，作为第一检测器输出信号的函数的值CLK或其补码/ CLK。 当时钟选通信号/ EN被断言时，第二个检测器保持门控时钟信号GCLK当时钟门控信号/ EN从解除断言转变为有效时所具有的值。

    LOW POWER INVERTER CIRCUIT
    6.
    发明申请
    LOW POWER INVERTER CIRCUIT 有权
    低功率逆变器电路

    公开(公告)号：US20150102839A1

    公开(公告)日：2015-04-16

    申请号：US14463673

    申请日：2014-08-20

    申请人： Amit Roy ,  Zhihong Cheng ,  Amit Kumar Dey ,  Vijay Tayal ,  Chetan Verma

    发明人： Amit Roy ,  Zhihong Cheng ,  Amit Kumar Dey ,  Vijay Tayal ,  Chetan Verma

    IPC分类号： H03K19/00 ,  H03K19/20 ,  H03K19/017

    CPC分类号： H03K19/0013 ,  H03K19/0016 ,  H03K19/003 ,  H03K19/017 ,  H03K19/01707 ,  H03K19/20

    摘要： A low power inverter circuit includes first and second transistors that receive an input signal at their gate terminals. The first and second transistors are connected by way of their source terminals to third and fourth transistors, respectively. The third and fourth transistors are connected in parallel with fifth and sixth transistors, respectively. The third and fourth transistors are continuously switched on, and the fifth and sixth transistors are controlled in such a way to reduce short circuit current flowing through the first and second transistors when the input signal transitions from one state to another.

    摘要翻译： 低功率逆变器电路包括在其栅极端子处接收输入信号的第一和第二晶体管。 第一和第二晶体管分别通过其源极端子连接到第三和第四晶体管。 第三和第四晶体管分别与第五和第六晶体管并联连接。 第三和第四晶体管被连续接通，并且当输入信号从一个状态转变到另一个状态时，第五和第六晶体管以这样的方式被控制，以减少流过第一和第二晶体管的短路电流。

    NFC sensor with power sleep mode
    9.
    发明授权
    NFC sensor with power sleep mode 有权
    具有电源睡眠模式的NFC传感器

    公开(公告)号：US09166653B2

    公开(公告)日：2015-10-20

    申请号：US14134584

    申请日：2013-12-19

    申请人： Chetan Verma

    发明人： Chetan Verma

    IPC分类号： H04B7/00 ,  H04B5/00 ,  G06F3/0488 ,  H04B1/68

    CPC分类号： H04B5/0031 ,  G06F1/1694 ,  G06F1/1698 ,  G06F1/3215 ,  G06F1/3228 ,  G06F3/017 ,  Y02D70/00 ,  Y02D70/144 ,  Y02D70/166 ,  Y02D70/26 ,  Y02D70/42

    摘要： This disclosure describes systems, methods, and computer-readable media related to near field communication (NFC) sensors with power sleep mode. In some embodiments, one or more motions of a user device may be detected. The one or more motions may be analyzed to identify a pre-defined motion of a user device. A wireless sensor of the user device may be enabled in response to the identified pre-defined motion. A wireless sensor-enabled device may be determined to be within a pre-determined distance. Data may be exchanged with the wireless sensor-enabled device. The wireless sensor may be disabled upon completion of the data exchange.

    摘要翻译： 本公开描述了与具有功率睡眠模式的近场通信（NFC）传感器相关的系统，方法和计算机可读介质。 在一些实施例中，可以检测用户设备的一个或多个运动。 可以分析一个或多个运动以识别用户设备的预定义运动。 可以响应于所识别的预定义运动来启用用户设备的无线传感器。 可以将无线传感器启用的设备确定为在预定距离内。 可以与启用无线传感器的设备交换数据。 完成数据交换后，无线传感器可能被禁用。

    MOS transistor with forward bulk-biasing circuit
    10.
    发明授权
    MOS transistor with forward bulk-biasing circuit 有权
    MOS晶体管具有正向体积偏置电路

    公开(公告)号：US08803591B1

    公开(公告)日：2014-08-12

    申请号：US14072809

    申请日：2013-11-06

    申请人： Amit Roy ,  Amit Kumar Dey ,  Kulbhushan Misri ,  Vijay Tayal ,  Chetan Verma

    发明人： Amit Roy ,  Amit Kumar Dey ,  Kulbhushan Misri ,  Vijay Tayal ,  Chetan Verma

    IPC分类号： H03K3/01 ,  G05F5/00 ,  H03K19/00 ,  G05F3/20

    CPC分类号： G05F5/00 ,  G05F3/205 ,  H03K19/0027

    摘要： Forward bulk biasing circuitry for PMOS and NMOS transistors is provided. The bulk biasing circuitry includes two N-type MOS transistors, two P-type MOS transistors, and two capacitors. The forward bias to a bulk terminal of a transistor increases a threshold voltage of a transistor, thereby reducing a transition time and improving the performance of the transistor. The forward bias is provided only when the transistor transitions from one state to another, thereby reducing leakage power dissipation during active and standby modes of an integrated circuit that includes the transistor.

    摘要翻译： 提供了用于PMOS和NMOS晶体管的正向体偏置电路。 体偏置电路包括两个N型MOS晶体管，两个P型MOS晶体管和两个电容器。 对晶体管的体积端子的正向偏压增加了晶体管的阈值电压，从而减小了转换时间并提高了晶体管的性能。 仅当晶体管从一种状态转变到另一种状态时，才提供正向偏压，从而在包括晶体管的集成电路的有源和待机模式期间减少漏电功率损耗。