Common pin for multi-die semiconductor package
    1.
    发明授权
    Common pin for multi-die semiconductor package 有权
    多芯片半导体封装的通用引脚

    公开(公告)号:US09196578B1

    公开(公告)日:2015-11-24

    申请号:US14459337

    申请日:2014-08-14

    Abstract: A semiconductor package has multiple dies and an interior power bar that extends within an interior space formed within the die flag between the dies. The bond pads located on the interior side of each die are wire-bonded to the interior power bar. Some embodiments may have more than two dies and/or more than one interior power bar between each pair of adjacent dies.

    Abstract translation: 半导体封装具有多个管芯和内部电源杆,其在形成在管芯之间的管芯标记内的内部空间内延伸。 位于每个模具的内侧的接合焊盘被引线接合到内部电源杆。 一些实施例可以在每对相邻的模具之间具有多于两个的模具和/或多于一个的内部功率杆。

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