公开(公告)号：US20230230917A1

公开(公告)日：2023-07-20

申请号：US18125529

申请日：2023-03-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myungsam KANG ,  Youngchan Ko ,  Kyungdon MUN

IPC: H01L23/522 ,  H01L23/31 ,  H01L23/00 ,  H01L23/36

CPC classification number: H01L23/5226 ,  H01L23/31 ,  H01L24/14 ,  H01L23/36 ,  H01L24/20 ,  H01L24/19

Abstract: A semiconductor package includes a redistribution substrate including a first redistribution layer; a semiconductor chip having a connection pad connected to the first redistribution layer; a vertical connection conductor electrically connected to the connection pad by the first redistribution layer; a core member having a first through-hole accommodating the semiconductor chip and a second through-hole accommodating the vertical connection conductor; an encapsulant filling the first and second through-holes; and a redistribution member including a second redistribution layer. The vertical connection conductor and the core member include a same material. A width of a lower surface of the vertical connection conductor is wider than that of an upper surface thereof, a width of a lower end of the first through-hole is narrower than that of an upper end thereof, and a width of a lower end of the second through-hole is narrower than that of an upper end thereof.

公开(公告)号：US20220254725A1

公开(公告)日：2022-08-11

申请号：US17731841

申请日：2022-04-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangkyu LEE ,  Jingu KIM ,  Kyungdon MUN ,  Shanghoon SEO ,  Jeongho LEE

IPC: H01L23/538 ,  H01L25/00 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L25/10

Abstract: A semiconductor package is disclosed. The semiconductor package includes a back-side wiring substrate and a front-side redistribution layer which are in parallel, and a connector, a semiconductor chip and an encapsulator which are between the back-side wiring substrate and the front-side redistribution layer. The encapsulator surrounds surfaces of the connector and the semiconductor chip. The back-side wiring substrate includes a core layer, a back-side via plug extending through the core layer, and a back-side redistribution layer on the back-side via plug.

公开(公告)号：US20250062241A1

公开(公告)日：2025-02-20

申请号：US18653116

申请日：2024-05-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyungdon MUN ,  Jihwang KIM ,  Sangjin BAEK ,  Kuwon LEE

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L23/427 ,  H01L25/18 ,  H10B80/00

Abstract: A semiconductor package includes: a first substrate; a bridge chip disposed on the first substrate and having a first region and a second region; an upper semiconductor chip disposed on the first region of the bridge chip; and conductive posts disposed on the second region of the bridge chip and spaced apart from the upper semiconductor chip, wherein the upper semiconductor chip is electrically connected to the conductive posts through the bridge chip.

公开(公告)号：US20240032310A1

公开(公告)日：2024-01-25

申请号：US18163378

申请日：2023-02-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungdon MUN

IPC: H10B80/00 ,  H01L23/538 ,  H01L23/00

CPC classification number: H10B80/00 ,  H01L23/5385 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/08145 ,  H01L2224/08225 ,  H01L24/16 ,  H01L2224/16227 ,  H01L24/32 ,  H01L2224/32225 ,  H01L24/73 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L24/33 ,  H01L2224/33181 ,  H01L24/17 ,  H01L2224/17181 ,  H01L2924/1431 ,  H01L2924/14361 ,  H01L2924/14511 ,  H01L2924/1443 ,  H01L2924/1441 ,  H01L2924/1437 ,  H01L2924/1432

Abstract: A semiconductor package may include a base wiring structure, a first bridge chip and a cache memory chip on the base wiring structure and spaced apart from each other in a horizontal direction, and logic semiconductor chips adjacent to each other on the first bridge chip and the cache memory chip. Logic semiconductor chips each may include a cache memory. The first bridge chip may overlap at least two of the logic semiconductor chips in a vertical direction and the first bridge chip may include first bridge wirings electrically connecting at least two of the logic semiconductor chips. The cache memory chip may overlap the cache memory of at least one of the logic semiconductor chips in the vertical direction and the cache memory chip may be electrically connected to the cache memory of at least one of the logic semiconductor chips.

公开(公告)号：US20240006262A1

公开(公告)日：2024-01-04

申请号：US18176695

申请日：2023-03-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungdon MUN ,  Eungkyu Kim ,  Hyeonseok Lee

IPC: H01L23/367 ,  H01L25/16 ,  H10B80/00 ,  H01L23/498 ,  H01L23/373

CPC classification number: H01L23/3677 ,  H01L25/165 ,  H10B80/00 ,  H01L23/49811 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/49866 ,  H01L23/3738 ,  H01L24/16

Abstract: A semiconductor package includes a first redistribution structure, a first die above the first redistribution structure, a second die above the first die, a heat dissipation unit on side surfaces of the first die or the second die, and a second redistribution structure above the second die. The semiconductor package includes a first post protruding from an upper surface of the first redistribution structure and extending to a lower surface of the second redistribution structure, a second post connecting the heat dissipation unit with a heat dissipation redistribution structure as a thermal path, and a molding unit filling an empty space between the first redistribution structure and the second redistribution structure. An outer pad of the heat dissipation redistribution structure is exposed to an outside of the semiconductor package, and an inner pad of the heat dissipation redistribution structure is in contact with the second post.

公开(公告)号：US20210233859A1

公开(公告)日：2021-07-29

申请号：US16990717

申请日：2020-08-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangkyu LEE ,  Jingu KIM ,  Kyungdon MUN ,  Shanghoon SEO ,  Jeongho LEE

IPC: H01L23/538 ,  H01L25/10 ,  H01L25/00 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683

Abstract: A semiconductor package is disclosed. The semiconductor package includes a back-side wiring substrate and a front-side redistribution layer which are in parallel, and a connector, a semiconductor chip and an encapsulator which are between the back-side wiring substrate and the front-side redistribution layer. The encapsulator surrounds surfaces of the connector and the semiconductor chip. The back-side wiring substrate includes a core layer, a back-side via plug extending through the core layer, and a back-side redistribution layer on the back-side via plug.

公开(公告)号：US20240063193A1

公开(公告)日：2024-02-22

申请号：US18210958

申请日：2023-06-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungdon MUN ,  Juhyeon KIM ,  Sangcheon PARK ,  Taeyoung LEE

IPC: H01L25/10 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L25/105 ,  H01L23/49827 ,  H01L24/08 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/80 ,  H01L2224/08145 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/8082 ,  H01L2924/1436 ,  H01L2924/1432

Abstract: A semiconductor package includes a first semiconductor chip including a first semiconductor substrate having a first active surface and a first inactive surface opposite to each other, a plurality of through electrodes penetrating the first semiconductor substrate, and a rear cover layer covering the first inactive surface, a second semiconductor chip stacked on the first semiconductor chip and including a second semiconductor substrate having a second active surface and a second inactive surface opposite to each other, and a front cover layer covering the second active surface, a plurality of signal pad structures penetrating the rear cover layer and the front cover layer to be electrically connected to the plurality of through electrodes, and a plurality of dummy pad structures apart from the plurality of signal pad structures in a horizontal direction, and penetrating the rear cover layer and the front cover layer.

公开(公告)号：US20240032312A1

公开(公告)日：2024-01-25

申请号：US18355004

申请日：2023-07-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taeyoung LEE ,  Kyungdon MUN

IPC: H10B80/00 ,  H01L25/065 ,  H01L23/00 ,  H01L23/538

CPC classification number: H10B80/00 ,  H01L25/0652 ,  H01L24/16 ,  H01L23/5384 ,  H01L2224/16227

Abstract: A semiconductor chip stack structure may include a buffer chip, a first memory chip on the buffer chip and including a plurality of first banks, a second memory chip on the first memory chip and including a plurality of second banks, first chiplets between the first memory chip and the second memory chip and configured to perform calculations on data stored in the plurality of first banks of the first memory chip, second chiplets between the first memory chip and the second memory chip and configured to perform calculations on data stored in the plurality of second banks of the second memory chip, and a third memory chip on the buffer chip. The third memory chip may include a plurality of third banks. The third memory chip may be electrically connected to the first memory chip and the second memory chip.

公开(公告)号：US20230187399A1

公开(公告)日：2023-06-15

申请号：US18166869

申请日：2023-02-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myungsam KANG ,  Youngchan KO ,  Jeongseok KIM ,  Kyungdon MUN

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/522

CPC classification number: H01L24/14 ,  H01L24/05 ,  H01L23/49811 ,  H01L23/5226

Abstract: A semiconductor package includes a redistribution structure including an insulating layer and a redistribution layer on the insulating layer, and having a first surface and a second surface opposing the first surface, and an under-bump metal (UBM) structure including an UBM pad protruding from the first surface of the redistribution structure, and an UBM via penetrating through the insulating layer and connecting the redistribution layer and the UBM pad. A lower surface of the UBM via has a first area in contact with the UBM pad, and a second area having a step configuration relative to the first area and that extends outwardly of the first area.

公开(公告)号：US20210265251A1

公开(公告)日：2021-08-26

申请号：US17031141

申请日：2020-09-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyungdon MUN ,  Myungsam KANG ,  Youngchan KO ,  Yieok KWON ,  Jeongseok KIM ,  Gongje LEE ,  Bongju CHO

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31

Abstract: A semiconductor package includes a core member having a first surface and a second surface opposing each other, and an external side surface between the first and second surfaces, the core member having a through-hole connecting the first and second surfaces, having a protruding portion that protrudes from the external side surface, and having a surface roughness (Ra) of 0.5 μm or more, a redistribution substrate on the first surface of the core member, and including a redistribution layer; a semiconductor chip in the through-hole on the redistribution substrate, and having a contact pad electrically connected to the redistribution layer, and an encapsulant on the redistribution substrate, and covering the semiconductor chip and the core member, the protruding portion of the core member having a surface exposed to a side surface of the encapsulant.