公开(公告)号：US20240063193A1

公开(公告)日：2024-02-22

申请号：US18210958

申请日：2023-06-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungdon MUN ,  Juhyeon KIM ,  Sangcheon PARK ,  Taeyoung LEE

IPC: H01L25/10 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L25/105 ,  H01L23/49827 ,  H01L24/08 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/80 ,  H01L2224/08145 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/8082 ,  H01L2924/1436 ,  H01L2924/1432

Abstract: A semiconductor package includes a first semiconductor chip including a first semiconductor substrate having a first active surface and a first inactive surface opposite to each other, a plurality of through electrodes penetrating the first semiconductor substrate, and a rear cover layer covering the first inactive surface, a second semiconductor chip stacked on the first semiconductor chip and including a second semiconductor substrate having a second active surface and a second inactive surface opposite to each other, and a front cover layer covering the second active surface, a plurality of signal pad structures penetrating the rear cover layer and the front cover layer to be electrically connected to the plurality of through electrodes, and a plurality of dummy pad structures apart from the plurality of signal pad structures in a horizontal direction, and penetrating the rear cover layer and the front cover layer.

公开(公告)号：US20240088006A1

公开(公告)日：2024-03-14

申请号：US18317521

申请日：2023-05-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangcheon PARK ,  Dongwoo KANG ,  Unbyoung KANG ,  Soohwan LEE ,  Hyunchul JUNG ,  Youngkun JEE

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/538

CPC classification number: H01L23/49827 ,  H01L23/5389 ,  H01L24/06 ,  H01L24/32 ,  H01L2224/0401 ,  H01L2224/06515 ,  H01L2224/32235 ,  H01L2924/1434

Abstract: Provided is a semiconductor package including a substrate including a first surface and a second surface opposite to the first surface, a connecting circuit arranged on the first surface of the substrate, a through silicon via (TSV) structure penetrating the substrate, a first passivation layer arranged on the connecting circuit, a second passivation layer arranged on the second surface, a first bumping pad arranged inside the first passivation layer, and a second bumping pad arranged inside the second passivation layer, wherein the first bumping pad includes a first pad plug, and a first seed layer surrounding a lower surface and sidewalls of the first pad plug, wherein the second bumping pad includes a second pad plug, and a second seed layer surrounding an upper surface and sidewalls of the second pad plug, and wherein the first seed layer and the second seed layer include materials having different reactivities to water.

公开(公告)号：US20220077116A1

公开(公告)日：2022-03-10

申请号：US17203909

申请日：2021-03-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangcheon PARK ,  Youngmin LEE

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/12 ,  H01L23/00

Abstract: A semiconductor package includes: a first structure having a first insulating layer disposed on one surface, and first electrode pads and first dummy pads penetrating through the first insulating layer, a second structure having a second insulating layer having the other surface bonded to the one surface and the first insulating layer and disposed on the other surface, and second electrode pads and second dummy pads that penetrate through the second insulating layer, the second electrode pads being bonded to the first electrode pads, respectively, and the second dummy pads being bonded to the first dummy pads, respectively. In the semiconductor chip, ratios of surface areas per unit area of the first and second dummy pads to the first and second insulating layers on the one surface and the other surface gradually decrease toward sides of the first and second structures.

公开(公告)号：US20240321923A1

公开(公告)日：2024-09-26

申请号：US18614335

申请日：2024-03-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Haeyeon CHUNG ,  Sangcheon PARK ,  Sungyong YOU ,  Sungsoo CHOI

IPC: H01L27/146 ,  H04N25/704

CPC classification number: H01L27/1463 ,  H01L27/14612 ,  H04N25/704

Abstract: An image sensor includes a substrate including a first pixel, a second pixel, a device isolation pattern, and at least one open region, wherein each of the first pixel and the second pixel includes a first pixel region including a first photoelectric conversion device and a second pixel region including a second photoelectric conversion device, the second pixel region being parallel with the first pixel region in a first direction, and wherein the device isolation pattern includes a first portion between the first pixel region and the second pixel region of the first pixel and between the first pixel region and the second pixel region of the second pixel, a second portion between the first pixel region of the first pixel and the first pixel region of the second pixel, and a third portion between the second pixel region of the first pixel and the second pixel region of the second pixel.

公开(公告)号：US20230361101A1

公开(公告)日：2023-11-09

申请号：US18356350

申请日：2023-07-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangcheon PARK ,  Youngmin LEE

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/48 ,  H01L23/522 ,  H01L23/544

CPC classification number: H01L25/18 ,  H01L24/08 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/544 ,  H01L2224/0224 ,  H01L2224/08145 ,  H01L2223/54426

Abstract: A semiconductor package includes: a first semiconductor chip including a plurality of front surface pads disposed on a first active surface of a first semiconductor substrate, at least one penetrating electrode penetrating at least a portion of the first semiconductor substrate and connected to the front surface pads, a first rear surface cover layer disposed on a first inactive surface of the first semiconductor substrate, a first rear surface dummy conductive layer penetrating a portion of the first rear surface cover layer; a second semiconductor chip including a second front surface cover layer disposed on a second active surface of a second semiconductor substrate, and a second front surface dummy conductive layer penetrating a portion of the second front surface cover layer; and at least one first bonded pad penetrating the first rear surface cover layer and the second front surface cover layer.

公开(公告)号：US20240413144A1

公开(公告)日：2024-12-12

申请号：US18808313

申请日：2024-08-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangcheon PARK ,  Youngmin Lee

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/48 ,  H01L23/522 ,  H01L23/544

Abstract: A semiconductor package includes: a first semiconductor chip including a plurality of front surface pads disposed on a first active surface of a first semiconductor substrate, at least one penetrating electrode penetrating at least a portion of the first semiconductor substrate and connected to the front surface pads, a first rear surface cover layer disposed on a first inactive surface of the first semiconductor substrate, a first rear surface dummy conductive layer penetrating a portion of the first rear surface cover layer; a second semiconductor chip including a second front surface cover layer disposed on a second active surface of a second semiconductor substrate, and a second front surface dummy conductive layer penetrating a portion of the second front surface cover layer; and at least one first bonded pad penetrating the first rear surface cover layer and the second front surface cover layer.

公开(公告)号：US20230215843A1

公开(公告)日：2023-07-06

申请号：US18174129

申请日：2023-02-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangcheon PARK ,  Youngmin Lee

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/00 ,  H01L23/12

CPC classification number: H01L25/0657 ,  H01L23/5385 ,  H01L24/06 ,  H01L23/12 ,  H01L23/5386

Abstract: A semiconductor package includes: a first structure having a first insulating layer disposed on one surface, and first electrode pads and first dummy pads penetrating through the first insulating layer, a second structure having a second insulating layer having the other surface bonded to the one surface and the first insulating layer and disposed on the other surface, and second electrode pads and second dummy pads that penetrate through the second insulating layer, the second electrode pads being bonded to the first electrode pads, respectively, and the second dummy pads being bonded to the first dummy pads, respectively. In the semiconductor chip, ratios of surface areas per unit area of the first and second dummy pads to the first and second insulating layers on the one surface and the other surface gradually decrease toward sides of the first and second structures.

公开(公告)号：US20230154910A1

公开(公告)日：2023-05-18

申请号：US17899025

申请日：2022-08-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunsoo CHUNG ,  Younglyong KIM ,  Sangcheon PARK

IPC: H01L25/18 ,  H01L23/48 ,  H01L23/00

CPC classification number: H01L25/18 ,  H01L23/481 ,  H01L24/08 ,  H01L24/05 ,  H01L24/80 ,  H01L2224/08145 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05644 ,  H01L2224/05639 ,  H01L2224/05666 ,  H01L2224/05686 ,  H01L2224/80379 ,  H01L2224/13147 ,  H01L24/13

Abstract: A semiconductor package includes a first semiconductor chip including a first substrate having a front surface and a rear surface, a first insulating layer on the rear surface, a recess portion extending into the first substrate through the first insulating layer, a protective insulating layer extending along an inner side surface and a bottom surface of the recess portion, a through electrode extending from the front surface through the bottom surface of the recess portion and the protective insulating layer, and a first connection pad contacting the through electrode in the recess portion, and surrounded by the protective insulating layer, the first semiconductor chip having a flat upper surface defined by upper surfaces of the first insulating layer, the protective insulating layer, the first connection pad; and a second semiconductor chip disposed on the upper surface of the first semiconductor chip.

公开(公告)号：US20250167179A1

公开(公告)日：2025-05-22

申请号：US19029388

申请日：2025-01-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangcheon PARK ,  Youngmin LEE

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/12 ,  H01L23/538

Abstract: A semiconductor package includes: a first structure having a first insulating layer disposed on one surface, and first electrode pads and first dummy pads penetrating through the first insulating layer, a second structure having a second insulating layer having the other surface bonded to the one surface and the first insulating layer and disposed on the other surface, and second electrode pads and second dummy pads that penetrate through the second insulating layer, the second electrode pads being bonded to the first electrode pads, respectively, and the second dummy pads being bonded to the first dummy pads, respectively. In the semiconductor chip, ratios of surface areas per unit area of the first and second dummy pads to the first and second insulating layers on the one surface and the other surface gradually decrease toward sides of the first and second structures.

公开(公告)号：US20240395764A1

公开(公告)日：2024-11-28

申请号：US18624233

申请日：2024-04-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Gyeongjae JO ,  Sangcheon PARK ,  Youngkun JEE

IPC: H01L23/00

Abstract: A bonding apparatus for a semiconductor device including: a substrate state having a seating surface on which a first semiconductor device is placed; a head portion having a lower surface, the head portion configured to hold a second semiconductor device on the lower surface to face the first semiconductor device, the lower surface including a first portion having a first height from the seating surface and a second portion having a second height from the seating surface, the second height being greater than the first height, the lower surface being inclined at an angle with respect to the seating surface; and a transfer portion provided on the head portion to move the head portion, the transfer portion configured to press the head portion from the first portion to the second portion such that the first and second semiconductor devices are bonded to each other.