公开(公告)号：US20250081462A1

公开(公告)日：2025-03-06

申请号：US18952236

申请日：2024-11-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hauk Han ,  Taeyong Kim ,  Keun Lee ,  Jeonggil Lee ,  Taisoo Lim ,  Hanmei Choi

IPC: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10

Abstract: A semiconductor device includes gate electrodes stacked and spaced apart from each other in a first direction perpendicular to an upper surface of a substrate; interlayer insulating layers alternately stacked with the gate electrodes on the substrate; channel structures extending through the gate electrodes; and a separation region extending through the gate electrodes in the first direction and extending in a second direction perpendicular to the first direction, wherein each of the gate electrodes comprises a first conductive layer and a second conductive layer sequentially stacked, the second conductive layer including a metal nitride, and wherein the first conductive layer and the second conductive layer are each in physical contact with the separation region.

公开(公告)号：US11744073B2

公开(公告)日：2023-08-29

申请号：US17530915

申请日：2021-11-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taisoo Lim ,  Kyungwook Park ,  Keun Lee ,  Hauk Han

IPC: H10B43/27 ,  H10B43/10 ,  H10B43/40 ,  H01L29/423 ,  H01L21/67 ,  H01L21/285 ,  H01L21/3213 ,  C23C16/56 ,  C23C16/455 ,  C23C16/06 ,  H01L21/28 ,  H01L21/02 ,  H01L29/66

CPC classification number: H10B43/27 ,  C23C16/06 ,  C23C16/45525 ,  C23C16/56 ,  H01L21/28568 ,  H01L21/32135 ,  H01L21/67069 ,  H01L29/40117 ,  H01L29/4234 ,  H10B43/10 ,  H10B43/40 ,  H01L21/02636 ,  H01L21/67167 ,  H01L29/66545

Abstract: A semiconductor device includes gate electrodes and interlayer insulating layers that are alternately stacked on a substrate, channel structures spaced apart from each other in a first direction and extending vertically through the gate electrodes and the interlayer insulating layers to the substrate, and a first separation region extending vertically through the gate electrodes and the interlayer insulating layers. Each gate electrode includes a first conductive layer and a second conductive layer, the first conductive layer disposed between the second conductive layer and each of two adjacent interlayer insulating layers. In a first region, between an outermost channel structure and the first separation region, of each gate electrode, the first conductive layer has a decreasing thickness toward the first separation region and the second conductive layer has an increasing thickness toward the first separation region.

公开(公告)号：US20190013388A1

公开(公告)日：2019-01-10

申请号：US16029993

申请日：2018-07-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hauk Han ,  Je-Hyeon Park ,  Do-hyung Kim ,  Tae-yong Kim ,  Keun Lee ,  Jeong-gil Lee ,  Hyun-seok Lim

IPC: H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L29/49 ,  H01L29/78

Abstract: A semiconductor memory device may include a substrate, gate electrode structures stacked on the substrate, insulation patterns between the gate electrode structures, vertical channels penetrating through the gate electrode structures and the insulation patterns, and a data storage pattern. The vertical channels may be electrically connected to the substrate. The data storage pattern may be arranged between the gate electrode structures and the vertical channels. Each of the gate electrode structures may include a barrier film, a metal gate, and a crystal grain boundary plugging layer. The crystal grain boundary plugging layer may be between the barrier film and the metal gate.

公开(公告)号：US20220077190A1

公开(公告)日：2022-03-10

申请号：US17530915

申请日：2021-11-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taisoo Lim ,  Kyungwook Park ,  Keun Lee ,  Hauk Han

IPC: H01L27/11582 ,  H01L29/423 ,  H01L21/67 ,  H01L27/11565 ,  H01L27/11573 ,  H01L21/285 ,  H01L21/3213 ,  C23C16/56 ,  C23C16/455 ,  C23C16/06 ,  H01L21/28

Abstract: A semiconductor device includes gate electrodes and interlayer insulating layers that are alternately stacked on a substrate, channel structures spaced apart from each other in a first direction and extending vertically through the gate electrodes and the interlayer insulating layers to the substrate, and a first separation region extending vertically through the gate electrodes and the interlayer insulating layers. Each gate electrode includes a first conductive layer and a second conductive layer, the first conductive layer disposed between the second conductive layer and each of two adjacent interlayer insulating layers. In a first region, between an outermost channel structure and the first separation region, of each gate electrode, the first conductive layer has a decreasing thickness toward the first separation region and the second conductive layer has an increasing thickness toward the first separation region.

公开(公告)号：US20210384217A1

公开(公告)日：2021-12-09

申请号：US17151383

申请日：2021-01-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hauk Han ,  Taeyong Kim ,  Keun Lee ,  Jeonggil Lee ,  Taisoo Lim ,  Hanmei Choi

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/11519 ,  H01L27/11556

Abstract: A semiconductor device includes gate electrodes stacked and spaced apart from each other in a first direction perpendicular to an upper surface of a substrate; interlayer insulating layers alternately stacked with the gate electrodes on the substrate; channel structures extending through the gate electrodes; and a separation region extending through the gate electrodes in the first direction and extending in a second direction perpendicular to the first direction, wherein each of the gate electrodes comprises a first conductive layer and a second conductive layer sequentially stacked, the second conductive layer including a metal nitride, and wherein the first conductive layer and the second conductive layer are each in physical contact with the separation region.

公开(公告)号：US20200303409A1

公开(公告)日：2020-09-24

申请号：US16700801

申请日：2019-12-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taisoo Lim ,  Kyungwook Park ,  Keun Lee ,  Hauk Han

IPC: H01L27/11582 ,  H01L29/423 ,  H01L21/67 ,  H01L27/11565 ,  H01L27/11573 ,  H01L21/285 ,  H01L21/28 ,  H01L21/3213 ,  C23C16/56 ,  C23C16/455 ,  C23C16/06

Abstract: A semiconductor device includes gate electrodes and interlayer insulating layers that are alternately stacked on a substrate, channel structures spaced apart from each other in a first direction and extending vertically through the gate electrodes and the interlayer insulating layers to the substrate, and a first separation region extending vertically through the gate electrodes and the interlayer insulating layers. Each gate electrode includes a first conductive layer and a second conductive layer, the first conductive layer disposed between the second conductive layer and each of two adjacent interlayer insulating layers. In a first region, between an outermost channel structure and the first separation region, of each gate electrode, the first conductive layer has a decreasing thickness toward the first separation region and the second conductive layer has an increasing thickness toward the first separation region.

公开(公告)号：US10680008B2

公开(公告)日：2020-06-09

申请号：US16000984

申请日：2018-06-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keun Lee ,  Jeong Gil Lee ,  Do Hyung Kim ,  Sung Nam Lyu ,  Hyun Seok Lim

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L21/768 ,  H01L23/532 ,  H01L21/02 ,  H01L21/28

Abstract: A method of manufacturing a semiconductor device includes alternately stacking sacrificial layers and interlayer insulating layers on a substrate, to form a stack structure; forming channels penetrating through the stack structure; forming separation regions penetrating through the stack structure; forming lateral openings by removing the sacrificial layers through the separation regions; and forming gate electrodes in the lateral openings. Forming the gate electrodes may include forming a nucleation layer in the lateral openings by supplying a source gas and a first reaction gas, and forming a bulk layer on the nucleation layer to fill the lateral openings by supplying the source gas and a second reaction gas, different from the first reaction gas. The first reaction gas may be supplied from a first reaction gas source, stored in a gas charging unit, and supplied from the gas charging unit.

公开(公告)号：US20190067429A1

公开(公告)日：2019-02-28

申请号：US15914113

申请日：2018-03-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keun Lee ,  Jeong Gil Lee ,  Do Hyung Kim ,  Ki Hyun Yoon ,  Hyun Seok Lim

IPC: H01L29/423 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/49 ,  H01L21/28

Abstract: Semiconductor devices and methods of forming the same are provided. Semiconductor devices may include a plurality of gate electrodes that are stacked on a substrate and are spaced apart from each other in a vertical direction and a channel region extending through the plurality of gate electrodes in the vertical direction. Each of the plurality of gate electrodes may include a first conductive layer defining a recess recessed toward the channel region, and a second conductive layer in the recess defined by the first conductive layer. A first concentration of impurities in the second conductive layer may be higher than a second concentration of the impurities in the first conductive layer, and the impurities may include nitrogen (N).

公开(公告)号：US10797143B2

公开(公告)日：2020-10-06

申请号：US15914113

申请日：2018-03-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keun Lee ,  Jeong Gil Lee ,  Do Hyung Kim ,  Ki Hyun Yoon ,  Hyun Seok Lim

IPC: H01L29/423 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/49 ,  H01L21/28 ,  G11C16/08 ,  G11C16/04

Abstract: Semiconductor devices and methods of forming the same are provided. Semiconductor devices may include a plurality of gate electrodes that are stacked on a substrate and are spaced apart from each other in a vertical direction and a channel region extending through the plurality of gate electrodes in the vertical direction. Each of the plurality of gate electrodes may include a first conductive layer defining a recess recessed toward the channel region, and a second conductive layer in the recess defined by the first conductive layer. A first concentration of impurities in the second conductive layer may be higher than a second concentration of the impurities in the first conductive layer, and the impurities may include nitrogen (N).

公开(公告)号：US11430665B2

公开(公告)日：2022-08-30

申请号：US16928548

申请日：2020-07-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taisoo Lim ,  Kyungwook Park ,  Wangyup Ryu ,  Keun Lee ,  Changwoo Lee ,  Hauk Han

IPC: C23C16/08 ,  H01L21/3205 ,  H01L21/285 ,  H01L21/673 ,  C23C16/455

Abstract: A method of manufacturing a semiconductor device may include forming a stack structure by alternately stacking sacrificial layers and interlayer insulating layers on a substrate, forming channel structures extending through the stack structure, forming openings extending through the stack structure, forming lateral openings by removing the sacrificial layers exposed by the openings, and forming gate electrodes in the lateral openings. Forming the gate electrodes may include supplying a source gas containing tungsten (W) wherein the source gas is heated to a first temperature and is supplied in a deposition apparatus at the first temperature, supplying a reactant gas containing hydrogen (H) subsequently to supplying the source gas, wherein the reactant gas is heated to a second temperature and is supplied in the deposition apparatus at the second temperature, and supplying a purge gas subsequently to supplying the reactant gas.