公开(公告)号：US11307608B2

公开(公告)日：2022-04-19

申请号：US16971049

申请日：2019-03-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minwoo Song ,  Younghyun Ban ,  Juyoung Lim ,  Chulmin Lee

IPC: G06F1/10 ,  G06F1/06 ,  H03K5/00

Abstract: Disclosed are an integrated circuit for controlling function modules to a low-power status depending on an operating status, an electronic device, and a control method thereof. An integrated circuit includes at least one clock generator, a clock distribution circuit that distributes a clock generated by the at least one clock generator, a plurality of function modules that receive the clock distributed by the clock distribution circuit, a monitoring circuit that monitors operating statuses of the at least one clock generator and the clock distribution circuit, a memory, and at least one control circuit. When the operating statuses of the at least one clock generator and the clock distribution circuit monitored by the monitoring circuit correspond to a specified operating status, the at least one control circuit is configured to control at least one of at least one function module of the plurality of function modules, the at least one clock generator, or the clock distribution circuit based on a specified control method. Moreover, various embodiment found through the disclosure are possible.

公开(公告)号：US11444098B2

公开(公告)日：2022-09-13

申请号：US16850244

申请日：2020-04-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Younghwan Son ,  Seungwon Lee ,  Seogoo Kang ,  Juyoung Lim ,  Jeehoon Han

IPC: H01L27/11582 ,  H01L29/51 ,  H01L29/49 ,  H01L23/528 ,  H01L23/522 ,  G11C16/10 ,  G11C16/04 ,  G11C16/26 ,  G11C11/56 ,  H01L27/11565 ,  H01L21/311 ,  H01L21/28

Abstract: A vertical non-volatile memory device includes a channel on a substrate and extending in a first direction perpendicular to an upper surface of the substrate, a first charge storage structure on an outer sidewall of the channel, a second charge storage structure on an inner sidewall of the channel, first gate electrodes spaced apart from each other in the first direction on the substrate, each which surrounds the first charge storage structure, and a second gate electrode on an inner sidewall of the second charge storage structure.

公开(公告)号：US20240355735A1

公开(公告)日：2024-10-24

申请号：US18419856

申请日：2024-01-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyemi LEE ,  Seungyoon Kim ,  Heesuk Kim ,  Sangjae Lee ,  Jaehoon Lee ,  Juyoung Lim ,  Minkyu Chung ,  Sanghun Chun ,  Jeehoon Han

IPC: H01L23/528 ,  H01L23/522 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00

CPC classification number: H01L23/5283 ,  H01L23/5226 ,  H01L25/0652 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00 ,  H01L2225/06506

Abstract: A semiconductor device includes a plate layer, gate electrodes and interlayer insulating layers alternately stacked on the plate layer in a first direction perpendicular to an upper surface of the plate layer and forming a first stack structure and a second stack structure on the first stack structure, a channel structure penetrating through the gate electrodes and extending in the first direction, and a contact plug extending in the first direction and electrically connected to one of the gate electrodes, wherein the second stack structure includes a first gate electrode on a lowermost portion, a first interlayer insulating layer on the first gate electrode, and a second interlayer insulating layer on the first interlayer insulating layer, and the first interlayer insulating layer has a first thickness, and the second interlayer insulating layer has a second thickness smaller than the first thickness.

公开(公告)号：US12002764B2

公开(公告)日：2024-06-04

申请号：US17529941

申请日：2021-11-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongsoo Kim ,  Juyoung Lim ,  Sunil Shim ,  Wonseok Cho

IPC: H01L23/544 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  G11C16/04

CPC classification number: H01L23/544 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  G11C16/0483 ,  H01L2223/54426

Abstract: An integrated circuit device comprising a base structure, a gate stack on the base structure and comprising a plurality of gate electrodes spaced apart from each other, a first upper insulating layer on the gate stack, a plurality of channel structures that penetrate the gate stack, each of the plurality of channel structures comprises a respective alignment key protruding from the gate stack, a second upper insulating layer that overlaps the respective alignment key of each of the plurality of channel structures, a top supporting layer on the second upper insulating layer, a bit line on the top supporting layer, and a plurality of bit line contacts that electrically connect respective ones of the plurality of channel structures to the bit line. A sidewall of the first upper insulating layer includes a first step.

公开(公告)号：US11910603B2

公开(公告)日：2024-02-20

申请号：US17225493

申请日：2021-04-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jesuk Moon ,  Juyoung Lim ,  Jongsoo Kim ,  Sunil Shim ,  Haemin Lee ,  Wonseok Cho

IPC: H10B43/27 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40

CPC classification number: H10B43/27 ,  H01L23/5283 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40

Abstract: A vertical memory device includes a gate electrode structure on a substrate, a channel extending through the gate electrode structure, and an etch stop layer on a sidewall of the gate electrode structure. The gate electrode structure includes gate electrodes spaced apart from each other in a first direction and stacked in a staircase shape. The channel includes a first portion and a second portion contacting the first portion. A lower surface of the second portion has a width less than a width of an upper surface of the first portion. The etch stop layer contacts at least one gate electrode of the gate electrodes, and overlaps an upper portion of the first portion of the channel in a horizontal direction. The at least one gate electrode contacting the etch stop layer is a dummy gate electrode including an insulating material.

公开(公告)号：US20220254807A1

公开(公告)日：2022-08-11

申请号：US17507929

申请日：2021-10-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongsoo KIM ,  Sunil Shim ,  Juyoung Lim ,  Wonseok Cho

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L23/528

Abstract: A semiconductor device including: a memory cell array region and a staircase region on a pattern structure; a stack structure including insulating layers and gate layers with gate pads alternately stacked in a vertical direction; a separation structure penetrating through the stack structure and contacting the pattern structure; a memory vertical structure penetrating through the stack structure and contacting the pattern structure; a support vertical structure penetrating through the stack structure and contacting the pattern structure; gate contact plugs disposed on the gate pads; and a peripheral contact plug spaced apart from the gate layers, wherein an upper surface of the memory vertical structure is at a first level, an upper surface of the peripheral contact plug is at a second level, an upper surface of the separation structure is at a third level, and upper surfaces of the gate contact plugs are at a fourth level.

公开(公告)号：US12262535B2

公开(公告)日：2025-03-25

申请号：US17507929

申请日：2021-10-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongsoo Kim ,  Sunil Shim ,  Juyoung Lim ,  Wonseok Cho

IPC: H10B43/27 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40

Abstract: A semiconductor device including: a memory cell array region and a staircase region on a pattern structure; a stack structure including insulating layers and gate layers with gate pads alternately stacked in a vertical direction; a separation structure penetrating through the stack structure and contacting the pattern structure; a memory vertical structure penetrating through the stack structure and contacting the pattern structure; a support vertical structure penetrating through the stack structure and contacting the pattern structure; gate contact plugs disposed on the gate pads; and a peripheral contact plug spaced apart from the gate layers, wherein an upper surface of the memory vertical structure is at a first level, an upper surface of the peripheral contact plug is at a second level, an upper surface of the separation structure is at a third level, and upper surfaces of the gate contact plugs are at a fourth level.

公开(公告)号：US12137560B2

公开(公告)日：2024-11-05

申请号：US17384329

申请日：2021-07-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： HangKyu Kang ,  Jongsoo Kim ,  Juyoung Lim ,  Wonseok Cho

IPC: H10B43/27 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40

Abstract: A semiconductor device includes a substrate having a first region, a second region, and a third region with gate electrodes spaced apart from each other in the first region and the second region. The semiconductor device also includes interlayer insulating layers alternately stacked with the gate electrodes, channel structures passing through the gate electrodes in the first region, first dummy structures passing through the gate electrodes in the second region, the first dummy structures disposed adjacent to the first region, second dummy structures passing through the gate electrodes in the second region, the second dummy structures disposed adjacent to the third region, and having different shapes from the first dummy structures, and support structures passing through the gate electrodes in the third region. A size of each of the second dummy structures is larger than a size of each of the support structures.

公开(公告)号：US11887936B2

公开(公告)日：2024-01-30

申请号：US17469952

申请日：2021-09-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kwanyong Kim ,  Sungwon Shin ,  Seungmin Lee ,  Juyoung Lim ,  Wonseok Cho

IPC: H01L23/544 ,  H01L23/532 ,  H01L23/528 ,  H10B41/46

CPC classification number: H01L23/544 ,  H01L23/5283 ,  H01L23/53295 ,  H10B41/46

Abstract: A semiconductor device includes a first stack structure on a substrate, and a second stack structure on the first stack structure. A channel structure extends through the first stack structure and the second stack structure. A first auxiliary stack structure including a plurality of first insulating layers and a plurality of first mold layers are alternately stacked on the substrate. An alignment key extends into the first auxiliary stack structure and protrudes to a higher level than an uppermost end of the first stack structure. A second auxiliary stack structure is disposed on the first auxiliary stack structure and the alignment key, and includes a plurality of second insulating layers and a plurality of second mold layers alternately stacked. The second auxiliary stack structure includes a protrusion aligned with the alignment key.

公开(公告)号：US11800712B2

公开(公告)日：2023-10-24

申请号：US17339129

申请日：2021-06-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juyeon Jung ,  Kwanyong Kim ,  Haemin Lee ,  Juyoung Lim ,  Wonseok Cho

IPC: H01L27/11582 ,  H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40

CPC classification number: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40

Abstract: A semiconductor memory device includes a substrate having a first region, a second region, and a third region main separation regions extending in the first direction and apart from each other in a second direction, first auxiliary separation regions extending in the first direction and spaced apart from each other in the second direction, and second auxiliary separation regions extending in the first direction and spaced apart from each other in the second direction. The first auxiliary separation regions are at a first pitch in the second direction between the main separation regions, the second auxiliary separation regions are disposed at a second pitch, smaller than the first pitch in the second direction between the main separation regions, and the first auxiliary separation regions and the second auxiliary separation regions are shifted from each other in the second direction.