公开(公告)号：US20220310594A1

公开(公告)日：2022-09-29

申请号：US17569363

申请日：2022-01-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youncheol Jeong ,  Jaeung Koo ,  Kwansung Kim ,  Seungyoon Kim ,  Boun Yoon ,  Jooho Jung ,  Sukbae Joo

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

Abstract: A semiconductor device includes an active region extending in a first direction on a substrate, a plurality of channel layers vertically spaced apart from each other on the active region, a gate structure vertically overlapping the active region and the plurality of channel layers on the substrate, extending in a second direction, and including a gate electrode surrounding the plurality of channel layers and a gate capping layer disposed on an upper surface of the gate electrode, a first source/drain region disposed on a side of the gate structure on the active region and in contact with the plurality of channel layers, an isolation structure intersecting the active region on the substrate, extending in the second direction, and disposed between the first source/drain region and a second source/drain region adjacent to each other, and contact structures in contact with the source/drain regions.

公开(公告)号：US20240355735A1

公开(公告)日：2024-10-24

申请号：US18419856

申请日：2024-01-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyemi LEE ,  Seungyoon Kim ,  Heesuk Kim ,  Sangjae Lee ,  Jaehoon Lee ,  Juyoung Lim ,  Minkyu Chung ,  Sanghun Chun ,  Jeehoon Han

IPC: H01L23/528 ,  H01L23/522 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00

CPC classification number: H01L23/5283 ,  H01L23/5226 ,  H01L25/0652 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00 ,  H01L2225/06506

Abstract: A semiconductor device includes a plate layer, gate electrodes and interlayer insulating layers alternately stacked on the plate layer in a first direction perpendicular to an upper surface of the plate layer and forming a first stack structure and a second stack structure on the first stack structure, a channel structure penetrating through the gate electrodes and extending in the first direction, and a contact plug extending in the first direction and electrically connected to one of the gate electrodes, wherein the second stack structure includes a first gate electrode on a lowermost portion, a first interlayer insulating layer on the first gate electrode, and a second interlayer insulating layer on the first interlayer insulating layer, and the first interlayer insulating layer has a first thickness, and the second interlayer insulating layer has a second thickness smaller than the first thickness.

公开(公告)号：US20250014997A1

公开(公告)日：2025-01-09

申请号：US18892906

申请日：2024-09-23

Applicant: Samsung electronics Co., Ltd.

Inventor： Seungyoon Kim ,  Jeongyong Sung ,  Sanghun Chun ,  Jihwan Kim ,  Sunghee Chung ,  Jeehoon Han

IPC: H01L23/528 ,  H01L29/423 ,  H10B43/27

Abstract: A semiconductor device includes a pattern structure; a stack structure including gate layers stacked in a first region on the pattern structure and extending into a second region; a memory vertical structure penetrating the stack structure in the first region; gate contact plugs electrically connected to the gate layers in the second region; and a first peripheral contact plug spaced apart from the gate layers, the gate layers including a first gate layer, the gate contact plugs including a first gate contact plug electrically connected to the first gate layer, side surfaces of the first gate contact plug and the first peripheral contact plug having different numbers of upper bending portions, and the number of upper bending portions of the side surface of the first gate contact plug being greater than the number of upper bending portions of the side surface of the first peripheral contact plug.

公开(公告)号：US20240090219A1

公开(公告)日：2024-03-14

申请号：US18231284

申请日：2023-08-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongseon AHN ,  Seungyoon Kim ,  Heesuk Kim ,  Yejin Park ,  Jaehwang Sim

IPC: H10B43/27 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/35 ,  H10B43/40

CPC classification number: H10B43/27 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/35 ,  H10B43/40

Abstract: A vertical memory device includes: a lower pad pattern disposed on a substrate; a cell stack structure disposed on the lower pad pattern and including first insulation layers and gate patterns, wherein the cell stack structure has a stepped shape; a through cell contact including a first through portion and a first protrusion, wherein the first through portion passes through a portion of the cell stack structure, and wherein the first protrusion protrudes from the first through portion and contacts an uppermost gate pattern of the gate patterns; and a first insulation pattern at least partially surrounding a sidewall, of the first through portion, that is below the first protrusion, wherein the first insulation pattern is longer than the first protrusion in a horizontal direction from the first through portion, and wherein a vertical thickness of the first protrusion is greater than a vertical thickness of the uppermost gate pattern.

公开(公告)号：US11791262B2

公开(公告)日：2023-10-17

申请号：US17475128

申请日：2021-09-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungyoon Kim ,  Jeongyong Sung ,  Sanghun Chun ,  Jihwan Kim ,  Sunghee Chung ,  Jeehoon Han

IPC: H01L23/528 ,  H01L29/423 ,  H10B43/27

CPC classification number: H01L23/5283 ,  H01L29/42356 ,  H10B43/27

Abstract: A semiconductor device includes a pattern structure; a stack structure including gate layers stacked in a first region on the pattern structure and extending into a second region; a memory vertical structure penetrating the stack structure in the first region; gate contact plugs electrically connected to the gate layers in the second region; and a first peripheral contact plug spaced apart from the gate layers, the gate layers including a first gate layer, the gate contact plugs including a first gate contact plug electrically connected to the first gate layer, side surfaces of the first gate contact plug and the first peripheral contact plug having different numbers of upper bending portions, and the number of upper bending portions of the side surface of the first gate contact plug being greater than the number of upper bending portions of the side surface of the first peripheral contact plug.

公开(公告)号：US20250100101A1

公开(公告)日：2025-03-27

申请号：US18732911

申请日：2024-06-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungyoon Kim ,  Eunkyoung Kim ,  Boumyoung Park ,  Hyodong Lee

IPC: B24B37/26

Abstract: A buffing treatment module includes: a buffing table that supports a substrate; a buffing head located on the buffing table and configured to rotate; and a buffing pad attached to a lower part of the buffing head and rotating while in contact with the substrate for performing buffing treatment on the substrate, wherein the buffing pad includes: a base unit; a plurality of protrusion units that protrude from a surface of the base unit and are spaced apart from each other in a circumferential direction of the base unit; and a plurality of trench units positioned adjacent to the plurality of protrusion units, and extending from a center portion of the base unit to an edge portion of the base unit, wherein the plurality of trench units are spaced apart from each other in the circumferential direction of the base unit.

公开(公告)号：US12131995B2

公开(公告)日：2024-10-29

申请号：US18370913

申请日：2023-09-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungyoon Kim ,  Jeongyong Sung ,  Sanghun Chun ,  Jihwan Kim ,  Sunghee Chung ,  Jeehoon Han

IPC: H10B43/27 ,  H01L23/528 ,  H01L29/423

CPC classification number: H01L23/5283 ,  H01L29/42356 ,  H10B43/27

Abstract: A semiconductor device includes a pattern structure; a stack structure including gate layers stacked in a first region on the pattern structure and extending into a second region; a memory vertical structure penetrating the stack structure in the first region; gate contact plugs electrically connected to the gate layers in the second region; and a first peripheral contact plug spaced apart from the gate layers, the gate layers including a first gate layer, the gate contact plugs including a first gate contact plug electrically connected to the first gate layer, side surfaces of the first gate contact plug and the first peripheral contact plug having different numbers of upper bending portions, and the number of upper bending portions of the side surface of the first gate contact plug being greater than the number of upper bending portions of the side surface of the first peripheral contact plug.

公开(公告)号：US12114504B2

公开(公告)日：2024-10-08

申请号：US17321747

申请日：2021-05-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungyoon Kim ,  Jaeryong Sim ,  Jeehoon Han

IPC: H10B43/50 ,  H01L21/768 ,  H01L23/535 ,  H10B41/27 ,  H10B41/41 ,  H10B41/50 ,  H10B43/27 ,  H10B43/40

CPC classification number: H10B43/50 ,  H01L21/76805 ,  H01L21/76895 ,  H01L23/535 ,  H10B41/27 ,  H10B41/41 ,  H10B41/50 ,  H10B43/27 ,  H10B43/40

Abstract: An integrated circuit device includes a substrate, a peripheral circuit structure disposed on the substrate, the peripheral circuit structure including a peripheral circuit and a lower wiring connected to the peripheral circuit, a conductive plate covering a portion of the peripheral circuit structure, a cell array structure disposed on the peripheral circuit structure with the conductive plate therebetween, the cell array structure including a memory cell array and an insulation layer surrounding the memory cell array, a through hole via passing through the insulation layer in a direction vertical to a top surface of the substrate to be connected to the lower wiring, and an etch guide member disposed in the insulation layer at the same level as the conductive plate to contact a portion of the through hole via.

公开(公告)号：US20220139831A1

公开(公告)日：2022-05-05

申请号：US17475128

申请日：2021-09-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungyoon Kim ,  Jeongyong Sung ,  Sanghun Chun ,  Jihwan Kim ,  Sunghee Chung ,  Jeehoon Han

IPC: H01L23/528 ,  H01L27/11582 ,  H01L29/423

Abstract: A semiconductor device includes a pattern structure; a stack structure including gate layers stacked in a first region on the pattern structure and extending into a second region; a memory vertical structure penetrating the stack structure in the first region; gate contact plugs electrically connected to the gate layers in the second region; and a first peripheral contact plug spaced apart from the gate layers, the gate layers including a first gate layer, the gate contact plugs including a first gate contact plug electrically connected to the first gate layer, side surfaces of the first gate contact plug and the first peripheral contact plug having different numbers of upper bending portions, and the number of upper bending portions of the side surface of the first gate contact plug being greater than the number of upper bending portions of the side surface of the first peripheral contact plug.

公开(公告)号：US12302570B2

公开(公告)日：2025-05-13

申请号：US17739845

申请日：2022-05-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kohji Kanamori ,  Seungyoon Kim ,  Jeehoon Han

IPC: H10B43/27 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40

Abstract: A semiconductor device includes a stack structure of alternating interlayer insulating layers and gate electrodes, a separation structure vertically penetrating the stack structure and extending in a first direction, to separate the gate electrodes in a second direction, and vertical structures vertically penetrating the stack structure and arranged at a constant pitch. The vertical structures are arranged along array lines sequentially arranged in the second direction away from a side of the separation structure in a plan view. The vertical structures include a channel structure including a channel layer, a contact structure including a metal plug having an upper surface on a level higher than that of an upper surface of the channel structure, and a dummy structure disposed adjacent to the contact structure. The channel structure, the dummy structure, and the contact structure are disposed to be aligned with each other on at least one of the array lines.