公开(公告)号：US09171729B2

公开(公告)日：2015-10-27

申请号：US14200680

申请日：2014-03-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byung-Kwan You ,  Kwang-Soo Seol ,  Young-woo Park ,  Jin-Soo Lim

IPC: H01L21/20 ,  H01L21/36 ,  H01L21/28 ,  H01L27/115 ,  H01L29/792 ,  H01L21/02

CPC classification number: H01L21/28282 ,  H01L21/02104 ,  H01L27/11582 ,  H01L29/7926

Abstract: Methods of manufacturing vertical semiconductor devices may include forming a mold structure including sacrificial layers and insulating interlayers with a first opening formed therethrough. The sacrificial layers and the insulating interlayers may be stacked repeatedly and alternately on a substrate. The first opening may expose the substrate. Blocking layers may be formed by oxidizing portions of the sacrificial layers exposed by the first opening. A first semiconductor layer pattern, a charge trapping layer pattern and a tunnel insulation layer pattern, respectively, may be formed on the sidewall of the first opening. A second semiconductor layer may be formed on the first polysilicon layer pattern and the bottom of the first opening. The sacrificial layers and the insulating interlayers may be partially removed to form a second opening. The sacrificial layers may be removed to form grooves between the insulating interlayers. Control gate electrodes may be formed in the grooves.

Abstract translation: 制造垂直半导体器件的方法可以包括形成包括牺牲层和绝缘夹层的模具结构，其中形成有第一开口。 牺牲层和绝缘夹层可以重复地和交替地层叠在基板上。 第一开口可能暴露基板。 可以通过氧化由第一开口暴露的牺牲层的部分来形成阻挡层。 分别可以在第一开口的侧壁上形成第一半导体层图案，电荷俘获层图案和隧道绝缘层图案。 可以在第一多晶硅层图案和第一开口的底部上形成第二半导体层。 可以部分去除牺牲层和绝缘夹层以形成第二开口。 可以去除牺牲层以在绝缘夹层之间形成凹槽。 控制栅电极可以形成在凹槽中。

公开(公告)号：US09553101B2

公开(公告)日：2017-01-24

申请号：US14258772

申请日：2014-04-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taekyung Kim ,  Kwang Soo Seol ,  Hyunchul Back ,  Jin-Soo Lim ,  Seong Soon Cho

IPC: H01L27/115 ,  H01L27/06 ,  H01L27/24 ,  H01L29/66 ,  H01L29/788 ,  H01L29/792 ,  H01L45/00

CPC classification number: H01L27/11578 ,  H01L27/0688 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11597 ,  H01L27/2409 ,  H01L27/2454 ,  H01L27/249 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926 ,  H01L45/04 ,  H01L45/06 ,  H01L45/10 ,  H01L45/1226 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/148

Abstract: A semiconductor device may include gate structures spaced apart above a top surface of a substrate. The gate structures may include a horizontal electrode extending in a first direction parallel with the top surface of a substrate. An isolation insulating layer may be disposed between the gate structures. A plurality of cell pillars may penetrate the horizontal electrode and connect to the substrate. The plurality of cell pillars may include a minimum spacing defined by a shortest distance between any two of the plurality of cell pillars. The thickness of the horizontal electrode may be greater than the minimum spacing of the cell pillars.

Abstract translation: 半导体器件可以包括在衬底的顶表面之上间隔开的栅极结构。 栅极结构可以包括在与衬底的顶表面平行的第一方向上延伸的水平电极。 隔离绝缘层可以设置在栅极结构之间。 多个单元柱可以穿透水平电极并连接到基板。 多个单元柱可以包括由多个单元柱中的任何两个之间的最短距离限定的最小间隔。 水平电极的厚度可以大于电池柱的最小间距。

公开(公告)号：US09240419B2

公开(公告)日：2016-01-19

申请号：US14515997

申请日：2014-10-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Il Chang ,  Changhyun Lee ,  Byoungkeun Son ,  Jin-Soo Lim

IPC: H01L21/00 ,  H01L27/115 ,  H01L29/423 ,  H01L21/822 ,  H01L27/06 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L27/11582 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/31111 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/11556 ,  H01L29/4232 ,  H01L29/42372

Abstract: Three-dimensional semiconductor devices are provided. The three-dimensional semiconductor device includes a substrate, a buffer layer on the substrate. The buffer layer includes a material having an etching selectivity relative to that of the substrate. A multi-layer stack including alternating insulation patterns and conductive patterns is provided on the buffer layer opposite the substrate. One or more active patterns respectively extend through the alternating insulation patterns and conductive patterns of the multi-layer stack and into the buffer layer. Related fabrication methods are also discussed.

Abstract translation: 提供三维半导体器件。 三维半导体器件包括衬底，衬底上的缓冲层。 缓冲层包括具有相对于衬底的蚀刻选择性的材料。 在与衬底相对的缓冲层上提供包括交替绝缘图案和导电图案的多层堆叠。 一个或多个有源图案分别延伸穿过多层堆叠的交替绝缘图案和导电图案并进入缓冲层。 还讨论了相关的制造方法。

公开(公告)号：USRE50089E1

公开(公告)日：2024-08-20

申请号：US17732950

申请日：2022-04-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Il Chang ,  Changhyun Lee ,  Byoungkeun Son ,  Jin-Soo Lim

IPC: H01L29/423 ,  H01L21/02 ,  H01L21/311 ,  H01L21/822 ,  H01L27/06 ,  H10B41/27 ,  H10B43/27

CPC classification number: H01L29/4232 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/31111 ,  H01L21/8221 ,  H01L27/0688 ,  H01L29/42372 ,  H10B41/27 ,  H10B43/27

Abstract: Three-dimensional semiconductor devices are provided. The three-dimensional semiconductor device includes a substrate, a buffer layer on the substrate. The buffer layer includes a material having an etching selectivity relative to that of the substrate. A multi-layer stack including alternating insulation patterns and conductive patterns is provided on the buffer layer opposite the substrate. One or more active patterns respectively extend through the alternating insulation patterns and conductive patterns of the multi-layer stack and into the buffer layer. Related fabrication methods are also discussed.

公开(公告)号：US09490130B2

公开(公告)日：2016-11-08

申请号：US14726648

申请日：2015-06-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jong In Yun ,  Jin-Soo Lim ,  Hansoo Kim ,  Sung-Hwan Jang ,  Youngwoo Park ,  Byoungkeun Son

IPC: H01L21/00 ,  H01L21/84 ,  H01L21/28 ,  H01L27/115 ,  H01L29/66 ,  H01L29/792 ,  H01L21/311

CPC classification number: H01L29/78 ,  H01L21/28282 ,  H01L21/31111 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/7926

Abstract: A method of manufacturing a three-dimensional semiconductor memory device comprises forming a thin layer structure by alternately stacking first and second material layers on a substrate, forming a penetration dent penetrating the thin layer structure and exposing a top surface of the substrate recessed by the penetration dent, forming a vertical insulation layer penetrating the thin layer structure to cover an inner wall of the penetration dent, forming a semiconductor pattern penetrating the vertical insulation layer at the penetration dent to be inserted into the substrate, and forming an oxide layer between the thin layer structure and the substrate by oxidizing a sidewall of the penetration dent.

Abstract translation: 一种制造三维半导体存储器件的方法包括通过在衬底上交替地堆叠第一和第二材料层来形成薄层结构，形成穿透薄层结构的穿透凹陷，并使基底凹陷的顶部表面露出 形成穿透薄层结构的垂直绝缘层以覆盖穿透凹陷的内壁，形成穿透穿孔凹陷处的垂直绝缘层的半导体图案，以插入到基板中，并且在薄的层间形成氧化物层 通过氧化渗透凹陷的侧壁来形成层状结构和基底。

公开(公告)号：US20230010192A1

公开(公告)日：2023-01-12

申请号：US17702400

申请日：2022-03-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Hwan Lee ,  Jin-Soo Lim

IPC: H01L23/544 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582 ,  H01L27/11573

Abstract: A non-volatile memory device and a non-volatile memory system comprising the same are provided. The non-volatile memory device includes a first stack in which a first conductive pattern and a first dielectric layer are alternately stacked in a first direction on a substrate, a second stack in which a second conductive pattern and a second dielectric layer are alternately stacked in the first direction on the first stack opposite the substrate, a first monitoring channel structure that penetrates the first stack in the first direction, and a second monitoring channel structure that penetrates the second stack in the first direction and is =on the first monitoring channel structure. A width of a top of the first monitoring channel structure opposite the substrate is smaller than a width of a bottom of the second monitoring channel structure adjacent the top of the first monitoring channel structure.

公开(公告)号：US20150037951A1

公开(公告)日：2015-02-05

申请号：US14515997

申请日：2014-10-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-IL Il Chang ,  Changhyun Lee ,  Byoungkeun Son ,  Jin-Soo Lim

IPC: H01L27/115 ,  H01L21/311 ,  H01L21/02

CPC classification number: H01L27/11582 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/31111 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/11556 ,  H01L29/4232 ,  H01L29/42372

Abstract: Three-dimensional semiconductor devices are provided. The three-dimensional semiconductor device includes a substrate, a buffer layer on the substrate. The buffer layer includes a material having an etching selectivity relative to that of the substrate. A multi-layer stack including alternating insulation patterns and conductive patterns is provided on the buffer layer opposite the substrate. One or more active patterns respectively extend through the alternating insulation patterns and conductive patterns of the multi-layer stack and into the buffer layer. Related fabrication methods are also discussed.

Abstract translation: 提供三维半导体器件。 三维半导体器件包括衬底，衬底上的缓冲层。 缓冲层包括具有相对于衬底的蚀刻选择性的材料。 在与衬底相对的缓冲层上提供包括交替绝缘图案和导电图案的多层堆叠。 一个或多个有源图案分别延伸穿过多层堆叠的交替绝缘图案和导电图案并进入缓冲层。 还讨论了相关的制造方法。