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    Methods of manufacturing vertical semiconductor devices
    2.
    发明授权
    Methods of manufacturing vertical semiconductor devices 有权
    制造垂直半导体器件的方法

    公开(公告)号：US09171729B2

    公开(公告)日：2015-10-27

    申请号：US14200680

    申请日：2014-03-07

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Byung-Kwan You ,  Kwang-Soo Seol ,  Young-woo Park ,  Jin-Soo Lim

    IPC: H01L21/20 ,  H01L21/36 ,  H01L21/28 ,  H01L27/115 ,  H01L29/792 ,  H01L21/02

    CPC classification number: H01L21/28282 ,  H01L21/02104 ,  H01L27/11582 ,  H01L29/7926

    Abstract: Methods of manufacturing vertical semiconductor devices may include forming a mold structure including sacrificial layers and insulating interlayers with a first opening formed therethrough. The sacrificial layers and the insulating interlayers may be stacked repeatedly and alternately on a substrate. The first opening may expose the substrate. Blocking layers may be formed by oxidizing portions of the sacrificial layers exposed by the first opening. A first semiconductor layer pattern, a charge trapping layer pattern and a tunnel insulation layer pattern, respectively, may be formed on the sidewall of the first opening. A second semiconductor layer may be formed on the first polysilicon layer pattern and the bottom of the first opening. The sacrificial layers and the insulating interlayers may be partially removed to form a second opening. The sacrificial layers may be removed to form grooves between the insulating interlayers. Control gate electrodes may be formed in the grooves.

    Abstract translation: 制造垂直半导体器件的方法可以包括形成包括牺牲层和绝缘夹层的模具结构，其中形成有第一开口。 牺牲层和绝缘夹层可以重复地和交替地层叠在基板上。 第一开口可能暴露基板。 可以通过氧化由第一开口暴露的牺牲层的部分来形成阻挡层。 分别可以在第一开口的侧壁上形成第一半导体层图案，电荷俘获层图案和隧道绝缘层图案。 可以在第一多晶硅层图案和第一开口的底部上形成第二半导体层。 可以部分去除牺牲层和绝缘夹层以形成第二开口。 可以去除牺牲层以在绝缘夹层之间形成凹槽。 控制栅电极可以形成在凹槽中。

    Gate structure in non-volatile memory device
    3.
    发明授权
    Gate structure in non-volatile memory device 有权
    非易失性存储器件中的门结构

    公开(公告)号：US08907398B2

    公开(公告)日：2014-12-09

    申请号：US14177693

    申请日：2014-02-11

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jang-Gn Yun ,  Jung-Dal Choi ,  Kwang-Soo Seol

    IPC: H01L21/48 ,  H01L29/66 ,  H01L21/28 ,  H01L27/115 ,  H01L29/792

    CPC classification number: H01L29/7926 ,  H01L21/28282 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/792

    Abstract: A gate structure of a non-volatile memory device and a method of forming the same including a tunnel oxide layer pattern, a charge trap layer pattern, a blocking dielectric layer pattern having the uppermost layer including a material having a first dielectric constant greater than that of a material included in the tunnel oxide layer pattern, and first and second conductive layer patterns. The gate structure includes a first spacer to cover at least the sidewall of the second conductive layer pattern. The gate structure includes a second spacer covering the sidewall of the first spacer and the sidewall of the first conductive layer pattern and including a material having a second dielectric constant equal to or greater than the first dielectric constant. In the non-volatile memory device including the gate structure, erase saturation caused by back tunneling is reduced.

    Abstract translation: 非易失性存储器件的栅极结构及其形成方法，其包括隧道氧化物层图案，电荷陷阱层图案，阻挡介电层图案，其最上层包括第一介电常数大于其的介电常数的材料。 包括在隧道氧化物层图案中的材料，以及第一和第二导电层图案。 栅极结构包括至少覆盖第二导电层图案的侧壁的第一间隔物。 栅极结构包括覆盖第一间隔物的侧壁和第一导电层图案的侧壁的第二间隔物，并且包括具有等于或大于第一介电常数的第二介电常数的材料。 在包括栅极结构的非易失性存储器件中，由于后部隧道引起的擦除饱和度降低。

    Memory devices capable of reducing lateral movement of charges
    4.
    发明授权
    Memory devices capable of reducing lateral movement of charges 有权
    能够减少电荷横向移动的存储器件

    公开(公告)号：US08686491B2

    公开(公告)日：2014-04-01

    申请号：US13705595

    申请日：2012-12-05

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kwang-Soo Seol

    IPC: H01L29/788 ,  H01L29/792

    CPC classification number: H01L29/42344 ,  H01L21/28282 ,  H01L27/1157 ,  H01L29/4234 ,  H01L29/792

    Abstract: The memory devices include a tunneling insulating layer disposed on a substrate, a charge storage layer disposed on the tunneling insulating layer, a blocking insulating layer disposed on the charge storage layer and a control gate electrode disposed on the blocking insulating layer. The control gate electrode may have an edge portion spaced farther apart from the blocking insulating layer than a central portion of the control gate electrode to concentrate charge density distribution on a central portion of a memory cell.

    Abstract translation: 存储器件包括设置在衬底上的隧道绝缘层，设置在隧道绝缘层上的电荷存储层，设置在电荷存储层上的阻挡绝缘层和设置在阻挡绝缘层上的控制栅电极。 与控制栅极的中心部分相比，控制栅电极可以具有与阻挡绝缘层相距更远的边缘部分，以将电荷密度分布集中在存储器单元的中心部分上。

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