公开(公告)号：US20220277801A1

公开(公告)日：2022-09-01

申请号：US17749607

申请日：2022-05-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sehwan PARK ,  Jinyoung KIM ,  Ilhan PARK ,  Kyoman KANG ,  Sangwan NAM

IPC: G11C29/50 ,  G11C29/44 ,  G11C7/10 ,  G11C8/18 ,  G11C16/28

Abstract: A non-volatile memory device includes a memory cell array including a plurality of memory blocks that includes a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, a row decoder configured to select one among the plurality of memory blocks, based on an address, a voltage generator configured to apply word line voltages corresponding to selected word lines and unselected word lines, among the plurality of word lines, page buffers connected to the plurality of bit lines and configured to read data from a memory cell connected to one among the selected word lines of the selected one among the plurality of memory blocks, and a control logic configured to control the row decoder, the voltage generator, and the page buffers.

公开(公告)号：US20240038309A1

公开(公告)日：2024-02-01

申请号：US18378540

申请日：2023-10-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinyoung KIM ,  Sehwan PARK ,  Ilhan PARK ,  Youngdeok SEO ,  Dongmin SHIN

IPC: G11C16/16 ,  G11C16/08 ,  G11C16/04 ,  G11C16/26 ,  G11C16/24

CPC classification number: G11C16/16 ,  G11C16/08 ,  G11C16/0433 ,  G11C16/26 ,  G11C16/24

Abstract: A memory device may include a memory block and a control circuit. The memory block may include a first sub-block and a second sub-block that are connected between a common source line and a plurality of bit lines and may be vertically stacked. The control circuit may be configured to select any one of the common source line and the plurality of bit lines as a transmission path of an erase voltage based on positions of the first sub-block and the second sub-block, and perform erase operations on the first sub-block and the second sub-block in units of sub-blocks.

公开(公告)号：US20220366964A1

公开(公告)日：2022-11-17

申请号：US17530911

申请日：2021-11-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Inho KANG ,  Ilhan PARK ,  Jinyoung CHUN

IPC: G11C11/4093 ,  G11C11/406 ,  G11C11/4094 ,  G11C11/4096 ,  G11C11/4074 ,  G11C7/10

Abstract: A page buffer circuit includes a plurality of page buffers connected to a plurality of bitlines. Each of the plurality of page buffers includes a bitline selection transistor configured to connect a corresponding bitline of the plurality of bitlines to a sensing node, a precharge circuit configured to precharge the sensing node, and a dynamic latch circuit configured to store data in a storage node. Each of the plurality of page buffers is configured to refresh the data stored in the storage node through charge sharing between the storage node and the sensing node.

公开(公告)号：US20220005539A1

公开(公告)日：2022-01-06

申请号：US17156801

申请日：2021-01-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinyoung KIM ,  Sehwan PARK ,  Ilhan PARK ,  Sangwan NAM

IPC: G11C29/42 ,  G11C29/44 ,  G11C29/18

Abstract: A controller including: control pins for providing control signals to a nonvolatile memory; a buffer memory configured to store first to third tables; and an error correction code (ECC) circuit configured to correct an error in first data read from the nonvolatile memory according to a first read command, wherein the first table stores first offset information, the second table stores second offset information, and the third table stores third offset information, wherein the third offset information corresponds to a history read level and is determined by the first and second offset information, and when the error of the first data is uncorrectable, an on-chip valley search operation is performed by the nonvolatile memory according to a second read command, detection information of the on-chip valley search operation is received according to a specific command, and the second offset information which corresponds to the detection information is generated.

公开(公告)号：US20210034251A1

公开(公告)日：2021-02-04

申请号：US16898935

申请日：2020-06-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byungyong CHOI ,  Doohyun KIM ,  Changkyu SEOL ,  Ilhan PARK

IPC: G06F3/06 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26

Abstract: A method of operating a memory controller, the method including performing a state shaping operation on received data based on state shaping information in response to a write request, the received data and the write request being received from a host, the state shaping information representing a memory cell characteristic corresponding to a memory cell group on which the received data is to be programmed, and the state shaping information being received from a memory device, and transmitting transformation data to the memory device, the transformation data being generated through the state shaping operation.

公开(公告)号：US20240029814A1

公开(公告)日：2024-01-25

申请号：US18374026

申请日：2023-09-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sehwan PARK ,  Jinyoung KIM ,  Ilhan PARK ,  Kyoman KANG ,  Sangwan NAM

IPC: G11C29/50 ,  G11C7/10 ,  G11C8/18 ,  G11C16/28 ,  G11C29/44

CPC classification number: G11C29/50004 ,  G11C7/1039 ,  G11C7/1045 ,  G11C7/1057 ,  G11C7/1084 ,  G11C8/18 ,  G11C16/28 ,  G11C29/44 ,  G11C2029/1202

Abstract: A non-volatile memory device includes a memory cell array including a plurality of memory blocks that includes a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, a row decoder configured to select one among the plurality of memory blocks, based on an address, a voltage generator configured to apply word line voltages corresponding to selected word lines and unselected word lines, among the plurality of word lines, page buffers connected to the plurality of bit lines and configured to read data from a memory cell connected to one among the selected word lines of the selected one among the plurality of memory blocks, and a control logic configured to control the row decoder, the voltage generator, and the page buffers.

公开(公告)号：US20230072218A1

公开(公告)日：2023-03-09

申请号：US17736395

申请日：2022-05-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minseok KIM ,  Junyong PARK ,  Doohyun KIM ,  Ilhan PARK

IPC: G11C16/34 ,  G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G11C16/16 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  G11C29/10

Abstract: In a method of reducing reliability degradation of a nonvolatile memory device, the nonvolatile memory device in which initial data having an initial threshold voltage distribution is stored in a plurality of memory cells connected to a plurality of wordlines is provided. Before a first process causing reliability degradation is performed, a first write operation is performed such that first data having a first threshold voltage distribution is stored into memory cells connected to first wordlines. The first wordlines have a degree of reliability degradation less than a reference value. Before the first process is performed, a second write operation is performed such that second data having a second threshold voltage distribution is stored into memory cells connected to second wordlines. The second wordlines have a degree of reliability degradation greater than or equal to the reference value.

公开(公告)号：US20220276802A1

公开(公告)日：2022-09-01

申请号：US17522578

申请日：2021-11-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngdeok SEO ,  Jinyoung KIM ,  Sehwan PARK ,  Ilhan PARK

IPC: G06F3/06

Abstract: A nonvolatile memory device includes a memory block including a memory area, an on-chip valley search (OVS) circuit performing an OVS sensing operation on the memory block, and a buffer memory storing at least one variation table including variation information of a threshold voltage of memory cells, obtained from the OVS sensing operation. A reading operation including an OVS sensing operation and a main sensing operation on the memory area is performed in response to a read command applied by a memory controller, the OVS sensing operation is performed at an OVS sensing level, and the main sensing operation is performed at a main sensing level reflecting the variation information. In the nonvolatile memory device, correction accuracy for deterioration of a word line threshold voltage may be improved, and a burden on a memory controller may be reduced.

公开(公告)号：US20220199164A1

公开(公告)日：2022-06-23

申请号：US17503197

申请日：2021-10-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinyoung KIM ,  Sehwan PARK ,  Ilhan PARK ,  Youngdeok SEO ,  Dongmin SHIN

IPC: G11C16/16 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  G11C16/04

Abstract: A memory device may include a memory block and a control circuit. The memory block may include a first sub-block and a second sub-block that are connected between a common source line and a plurality of bit lines and may be vertically stacked. The control circuit may be configured to select any one of the common source line and the plurality of bit lines as a transmission path of an erase voltage based on positions of the first sub-block and the second sub-block, and perform erase operations on the first sub-block and the second sub-block in units of sub-blocks.