公开(公告)号：US20210201963A1

公开(公告)日：2021-07-01

申请号：US17200246

申请日：2021-03-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinyoung CHUN

IPC: G11C7/10 ,  G11C7/12 ,  G11C11/4074 ,  G11C7/22

Abstract: A page buffer includes a charging circuit, first and second storage circuits, and a selection circuit. The charging circuit charges a bit line during a precharging period. The first storage circuit determines and stores data corresponding to a state of a selected memory cell among memory cells connected to the bit line while the charging circuit charges the bit line. The second storage circuit, which is a circuit separate from the first storage circuit, determines and stores data corresponding to a state of the selected memory cell after the precharging period. The selection circuit outputs a control voltage controlling a switch element connected between the bit line and the charging circuit, and determines a magnitude of the control voltage during the precharging period, based on the data stored in the first storage circuit.

公开(公告)号：US20220366964A1

公开(公告)日：2022-11-17

申请号：US17530911

申请日：2021-11-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Inho KANG ,  Ilhan PARK ,  Jinyoung CHUN

IPC: G11C11/4093 ,  G11C11/406 ,  G11C11/4094 ,  G11C11/4096 ,  G11C11/4074 ,  G11C7/10

Abstract: A page buffer circuit includes a plurality of page buffers connected to a plurality of bitlines. Each of the plurality of page buffers includes a bitline selection transistor configured to connect a corresponding bitline of the plurality of bitlines to a sensing node, a precharge circuit configured to precharge the sensing node, and a dynamic latch circuit configured to store data in a storage node. Each of the plurality of page buffers is configured to refresh the data stored in the storage node through charge sharing between the storage node and the sensing node.

公开(公告)号：US20200381024A1

公开(公告)日：2020-12-03

申请号：US16738598

申请日：2020-01-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinyoung CHUN

IPC: G11C7/10 ,  G11C7/12 ,  G11C7/22 ,  G11C11/4074

Abstract: A page buffer includes a charging circuit, first and second storage circuits, and a selection circuit. The charging circuit charges a bit line during a precharging period. The first storage circuit determines and stores data corresponding to a state of a selected memory cell among memory cells connected to the bit line while the charging circuit charges the bit line. The second storage circuit, which is a circuit separate from the first storage circuit, determines and stores data corresponding to a state of the selected memory cell after the precharging period. The selection circuit outputs a control voltage controlling a switch element connected between the bit line and the charging circuit, and determines a magnitude of the control voltage during the precharging period, based on the data stored in the first storage circuit.