公开(公告)号：US20230135639A1

公开(公告)日：2023-05-04

申请号：US17888647

申请日：2022-08-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Keun LEE ,  Kihyun YOON ,  Jeonggil LEE ,  Hauk HAN

IPC: H01L27/11556 ,  H01L29/423

Abstract: An electrode structure includes a conductive electrode, the conductive electrode including a first surface, an insulating layer on the conductive electrode, the insulating layer being in contact with the first surface of the conductive electrode, and a nano dot pattern in the conductive electrode and spaced apart from the first surface of the conductive electrode, the nano dot pattern including nano dots arranged in parallel to the first surface of the conductive electrode, and each of the nano dots including a first side surface adjacent to the first surface of the conductive electrode, the first side surface being flat and parallel to the first surface of the conductive electrode, and a second side surface opposite to the first side surface, the second side surface being convex in a direction away from the first surface of the conductive electrode.

公开(公告)号：US20180358379A1

公开(公告)日：2018-12-13

申请号：US16108173

申请日：2018-08-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hauk HAN ,  Je-Hyeon PARK ,  Kihyun YOON ,  Changwon LEE ,  HyunSeok LIM ,  Jooyeon HA

IPC: H01L27/11582 ,  H01L23/535 ,  H01L27/1157

CPC classification number: H01L27/11582 ,  H01L21/76847 ,  H01L21/76856 ,  H01L21/76862 ,  H01L21/76876 ,  H01L21/76877 ,  H01L23/53266 ,  H01L23/535 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575

Abstract: A semiconductor device includes a lower structure including a lower conductor, an upper structure having an opening exposing the lower conductor on the lower structure, and a connection structure filling the opening and connected to the lower conductor. The connection structure includes a first tungsten layer covering an inner surface of the opening and defining a recess region in the opening, and a second tungsten layer filling the recess region on the first tungsten layer. A grain size of the second tungsten layer in an upper portion of the connection structure is greater than a grain size of the second tungsten layer in a lower portion of the connection structure.

公开(公告)号：US20140264498A1

公开(公告)日：2014-09-18

申请号：US14204441

申请日：2014-03-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hauk HAN ,  Il-Woo KIM ,  Jeong-Gil LEE ,  Yong-Il KWON ,  Myoung-Bum LEE

IPC: H01L29/78 ,  H01L21/28

CPC classification number: H01L29/78 ,  H01L21/76805 ,  H01L21/76831 ,  H01L27/11529 ,  H01L29/66825

Abstract: A memory device includes a gate structure, a contact plug, and a spacer. The gate structure includes first and second conductive layer patterns sequentially stacked on a substrate. The contact plug passes through the second conductive layer pattern, and a sidewall of the contact plug directly contacts at least a portion of the second conductive layer pattern. The spacer surrounds a portion of the sidewall of the contact plug and contacting the gate structure.

Abstract translation: 存储器件包括栅极结构，接触插塞和间隔物。 栅极结构包括顺序地堆叠在衬底上的第一和第二导电层图案。 接触插塞穿过第二导电层图案，并且接触插塞的侧壁直接接触第二导电层图案的至少一部分。 间隔件围绕接触塞的侧壁的一部分并接触门结构。

公开(公告)号：US20160329342A1

公开(公告)日：2016-11-10

申请号：US15096413

申请日：2016-04-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hauk HAN ,  Yeon-Sil SOHN

IPC: H01L27/115 ,  H01L29/06 ,  H01L29/51 ,  H01L29/792 ,  H01L29/49

CPC classification number: H01L29/792 ,  H01L27/1157 ,  H01L29/66833

Abstract: A semiconductor device includes a charge storage pattern on a substrate, a blocking insulating pattern on the charge storage pattern, and a control gate structure on the blocking insulating pattern, the control gate structure having a metal electrode pattern, and an oxidation prevention pattern on the metal electrode pattern, the oxidation prevention pattern including a metallic nitride.

Abstract translation: 半导体器件包括在基板上的电荷存储图案，电荷存储图案上的阻挡绝缘图案，以及阻挡绝缘图案上的控制栅极结构，具有金属电极图案的控制栅极结构和氧化防止图案 金属电极图案，氧化防止图案包括金属氮化物。

公开(公告)号：US20140015030A1

公开(公告)日：2014-01-16

申请号：US13940721

申请日：2013-07-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hauk HAN ,  Yong-IL KWON ,  JungSuk OH ,  Tae sun RYU ,  Jeonggil LEE

IPC: H01L29/788 ,  H01L23/52

CPC classification number: H01L27/11531 ,  H01L21/28273 ,  H01L23/52 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11536 ,  H01L27/11539 ,  H01L29/42328 ,  H01L29/4238 ,  H01L29/4941 ,  H01L29/788 ,  H01L29/7881 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a lower insulating pattern on a semiconductor substrate, a lower gate pattern on the lower insulating pattern and formed of a doped polysilicon layer, a residual insulating pattern with an opening exposing a portion of a top surface of the lower gate pattern, an upper gate pattern on the residual insulating pattern, the upper gate pattern filling the opening, and a diffusion barrier pattern in contact with the portion of the top surface of the lower gate pattern and extending between the residual insulating pattern and the upper gate pattern.

Abstract translation: 半导体器件包括在半导体衬底上的下绝缘图案，下绝缘图案上的下栅极图案和由掺杂多晶硅层形成的残留绝缘图案，具有露出下栅极图案的顶表面的一部分的开口， 剩余绝缘图案上的上栅极图案，填充开口的上栅极图案，以及与下栅极图案的顶表面的部分接触并在残留绝缘图案和上栅极图案之间延伸的扩散阻挡图案。

公开(公告)号：US20240130126A1

公开(公告)日：2024-04-18

申请号：US18349460

申请日：2023-07-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeong Dong MUN ,  Seong Hun PARK ,  Hauk HAN ,  Seong Jin KIM

IPC: H10B43/27 ,  H10B43/35

CPC classification number: H10B43/27 ,  H10B43/35

Abstract: A non-volatile memory device including a substrate including a first area and a second area, a mold structure on the substrate, the mold structure including gate electrodes and mold insulating films alternately stacked on each other in a stepwise manner, an interlayer insulating film covering the mold structure, a channel structure on the first area, the channel structure extending through the mold structure and connected to the gate electrodes, and a through-contact on the second area and extending through the interlayer insulating film, the through-contact including a first portion in a first trench and a second portion in a second trench, the first portion including a liner film along a sidewall and a bottom surface of the first trench and a filling film on the liner film, wherein the filling film being a multi-grain conductive material, and the second portion being a single grain conductive material, may be provided.

公开(公告)号：US20220037351A1

公开(公告)日：2022-02-03

申请号：US17206277

申请日：2021-03-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeonggil LEE ,  Taisoo LIM ,  Hauk HAN

IPC: H01L27/11575 ,  H01L21/768 ,  H01L23/535 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582 ,  H01L27/11573

Abstract: A semiconductor device includes circuit elements on a first substrate; gate electrodes on a second substrate and stacked to be apart from each other in a first direction; sacrificial insulating layers on a lower through-insulating layer penetrating the second substrate, stacked to be spaced apart from each other in the first direction, and having side surfaces opposing the gate electrodes; channel structures penetrating the gate electrodes, extending vertically on the second substrate, and including a channel layer; a first separation pattern penetrating the gate electrodes and including a first barrier pattern and a first pattern portion extending from the first barrier pattern in a second direction; and a second separation pattern penetrating the gate electrodes, disposed to be parallel to the first separation pattern, and extending in the second direction. Some of the side surfaces of the sacrificial insulating layers may overlap the first barrier pattern in a third direction.

公开(公告)号：US20230343706A1

公开(公告)日：2023-10-26

申请号：US18158692

申请日：2023-01-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hauk HAN ,  Seonghun PARK ,  Jeonggil LEE

IPC: H01L23/528 ,  H01L23/532

CPC classification number: H01L23/5283 ,  H01L23/53266

Abstract: A semiconductor device includes an insulating structure, a first conductive structure in the insulating structure, the first conductive structure including a first conductive layer and a second conductive layer, and a second conductive structure in the insulating structure, the second conductive structure including a first conductive layer of the second conductive structure. A width of the first conductive structure is larger than a width of the second conductive structure. The first conductive layer of the first conductive structure, the second conductive layer of the first conductive structure, and the first conductive layer of the second conductive structure include a same nonmetal element. A concentration of the nonmetal element in the second conductive layer of the first conductive structure is higher than a concentration of the nonmetal element in the first conductive layer of the first conductive structure and first conductive layer of the second conductive structure.

公开(公告)号：US20210265373A1

公开(公告)日：2021-08-26

申请号：US17034274

申请日：2020-09-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shinjae KANG ,  Woosung LEE ,  Jeonggil LEE ,  Hanmei CHOI ,  Hauk HAN

IPC: H01L27/11556 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11582 ,  H01L23/522

Abstract: Semiconductor devices including a substrate including a cell array region and a through electrode region, an electrode stack on the substrate and including electrodes, vertical structures penetrating the electrode stack within the cell array region, vertical fence structures within an extension region and surrounding the through electrode region, and insulating layers being inside a perimeter defined by the vertical fence structures and being at the same level as the electrodes may be provided. The electrodes may include first protrusions protruding between the vertical fence structures in a plan view.

公开(公告)号：US20210159086A1

公开(公告)日：2021-05-27

申请号：US16928548

申请日：2020-07-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taisoo LIM ,  Kyungwook PARK ,  Wangyup RYU ,  Keun LEE ,  Changwoo LEE ,  Hauk HAN

IPC: H01L21/3205 ,  H01L21/285 ,  H01L21/673

Abstract: A method of manufacturing a semiconductor device may include forming a stack structure by alternately stacking sacrificial layers and interlayer insulating layers on a substrate, forming channel structures extending through the stack structure, forming openings extending through the stack structure, forming lateral openings by removing the sacrificial layers exposed by the openings, and forming gate electrodes in the lateral openings. Forming the gate electrodes may include supplying a source gas containing tungsten (W) wherein the source gas is heated to a first temperature and is supplied in a deposition apparatus at the first temperature, supplying a reactant gas containing hydrogen (H) subsequently to supplying the source gas, wherein the reactant gas is heated to a second temperature and is supplied in the deposition apparatus at the second temperature, and supplying a purge gas subsequently to supplying the reactant gas.