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    METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE
    4.
    发明申请
    METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE 有权
    制造半导体器件的方法

    公开(公告)号：US20160359020A1

    公开(公告)日：2016-12-08

    申请号：US15131611

    申请日：2016-04-18

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kyungin CHOI ,  Dongwoo KIM ,  Chang Woo SOHN ,  Youngmoon CHOI

    IPC: H01L29/66 ,  H01L21/3065 ,  H01L29/78 ,  H01L29/161 ,  H01L29/165

    CPC classification number: H01L29/66795 ,  H01L21/3065 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/7848

    Abstract: A method for manufacturing a semiconductor device includes forming a fin structure extending in a first direction on a substrate, forming a sacrificial gate pattern extending in a second direction to intersect the fin structure, forming a gate spacer layer covering the fin structure and the sacrificial gate pattern, providing a first ion beam having a first incident angle range and a second ion beam having a second incident angle range to the substrate, patterning the gate spacer layer using the first ion beam and the second ion beam to form gate spacers on sidewalls of the sacrificial gate pattern, forming source/drain regions at both sides of the sacrificial gate patterns, and replacing the sacrificial gate pattern with a gate electrode.

    Abstract translation: 一种制造半导体器件的方法包括：形成在衬底上沿第一方向延伸的翅片结构，形成沿第二方向延伸以与鳍结构相交的牺牲栅极图案，形成覆盖鳍结构的栅极间隔层和牺牲栅极 提供具有第一入射角范围的第一离子束和具有第二入射角范围的第二离子束到衬底，使用第一离子束和第二离子束来构图栅极间隔层，以在第二离子束的侧壁上形成栅极间隔 牺牲栅极图案，在牺牲栅极图案的两侧形成源极/漏极区域，以及用栅极电极代替牺牲栅极图案。

    GATE STRUCTURE OF VERTICAL FET AND METHOD OF MANUFACTURING THE SAME
    5.
    发明申请
    GATE STRUCTURE OF VERTICAL FET AND METHOD OF MANUFACTURING THE SAME 有权

    公开(公告)号：US20220123143A1

    公开(公告)日：2022-04-21

    申请号：US17563608

    申请日：2021-12-28

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Seung Hyun SONG ,  Chang Woo SOHN ,  Young Chai JUNG ,  Sa Hwan HONG

    IPC: H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/40 ,  H01L29/51 ,  H01L29/66

    Abstract: A vertical field-effect transistor (VFET) device and a method of manufacturing the same are provided. The VFET device includes: a fin structure formed on a substrate; a gate structure including a gate dielectric layer formed on an upper portion of a sidewall of the fin structure, and a conductor layer formed on a lower portion of the gate dielectric layer; a top source/drain (S/D) region formed above the fin structure and the gate structure; a bottom S/D region formed below the fin structure and the gate structure; a top spacer formed on an upper portion of the gate dielectric layer, and between the top S/D region and a top surface of the conductor layer; and a bottom spacer formed between the gate structure and the bottom S/D region. A top surface of the gate dielectric layer is positioned at the same or substantially same height as or positioned lower than a top surface of the top spacer, and higher than the top surface of the conductor layer.

    SEMICONDUCTOR DEVICE
    6.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20220115506A1

    公开(公告)日：2022-04-14

    申请号：US17335413

    申请日：2021-06-01

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sang Hoon LEE ,  Chang Woo SOHN ,  Keun Hwi CHO ,  Sang Won BAEK

    IPC: H01L29/417 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45 ,  H01L29/49 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786 ,  H01L21/02 ,  H01L21/285 ,  H01L21/8234 ,  H01L29/66

    Abstract: A semiconductor device includes first and second isolation regions, a first active region extending in a first direction between the first and second isolation regions, a first fin pattern on the first active region, nanowires on the first fin pattern, a gate electrode in a second direction on the first fin pattern, the gate electrode surrounding the nanowires, a first source/drain region on a side of the gate electrode, the first source/drain region being on the first active region and in contact with the nanowires, and a first source/drain contact on the first source/drain region, the first source/drain contact including a first portion on a top surface of the first source/drain region, and a second portion extending toward the first active region along a sidewall of the first source/drain region, an end of the first source/drain contact being on one of the first and second isolation regions.

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