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1.发明申请公开(公告)号：US20180053554A1
公开(公告)日：2018-02-22
申请号：US15681479
申请日：2017-08-21
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： SANG-WAN NAM , DAESEOK BYEON , CHIWEON YOON
CPC classification number: G11C16/08 , G11C16/0408 , G11C16/0483 , G11C16/107 , G11C16/26 , G11C16/28 , G11C16/3459 , G11C2216/16
Abstract: A nonvolatile memory device includes a memory cell array and a row decoder circuit. The row decoder circuit turns on memory cells of a plurality of cell strings of a selected memory block after applying a first prepulse to a first dummy word line connected to first dummy memory cells after applying a second prepulse to a second dummy word line connected to second dummy memory cells.
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公开(公告)号：US20240128935A1
公开(公告)日：2024-04-18
申请号：US18221128
申请日：2023-07-12
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jehoon KIM , DONGHO SHIN , JUNG-JUNE PARK , HYUNSUK KANG , CHIWEON YOON
CPC classification number: H03F1/30 , H03F3/45076 , H03F2203/45664
Abstract: A differential signaling circuit is provided. The differential signaling circuit includes: a differential amplifier configured to generate differential signals; a first signal path circuit; a second signal path circuit; a phase control circuit configured to receive the differential signals having a common phase, output DC signals having a common level in a first operating period, and transmit the differential signals to the first signal path circuit and the second signal path circuit, respectively, in a second operating period; and a duty ratio correction circuit connected between the first signal path circuit and the second signal path circuit, and configured to control duty ratios of the differential signals to be equal to each other in the second operating period.
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公开(公告)号：US20210349660A1
公开(公告)日：2021-11-11
申请号：US17030635
申请日：2020-09-24
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： TONGSUNG KIM , JANGWOO LEE , SEONKYOO LEE , CHIWEON YOON , JEONGDON IHM
Abstract: A storage device includes NVM package and a controller connected to the NVM package through a channel and controlling operation of the NVM package. The NVM package includes an interface chip, first NVM devices connected to the interface chip through a first internal channel and second NVM devices connected to the interface chip through a second internal channel. The interface chip selects the first internal channel in response to an operation request received from the controller and connects the first internal channel to the channel. The interface chip also determines whether retraining is necessary in relation to the second internal channel and transmits a retraining request to the controller when retraining is necessary.
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公开(公告)号：US20230342085A1
公开(公告)日：2023-10-26
申请号：US18217063
申请日：2023-06-30
Applicant: Samsung Electronics Co., Ltd.
Inventor： SEONKYOO LEE , JEONGDON IHM , CHIWEON YOON , BYUNGHOON JEONG
CPC classification number: G06F3/0659 , G06F1/06 , G06F3/0613 , G06F3/0679 , G06F13/1668 , G11C16/0483 , G11C16/10 , G11C16/26
Abstract: A nonvolatile memory device includes a first pin that receives a first signal, a second pin that receives a second signal, third pins that receive third signals, a fourth pin that receives a write enable signal, a memory cell array, and a memory interface circuit that obtains a command, an address, and data from the third signals in a first mode and obtains the command and the address from the first signal and the second signal and the data from the third signals in a second mode. In the first mode, the memory interface circuit obtains the command from the third signals and obtains the address from the third signals. In the second mode, the memory interface circuit obtains the command from the first signal and the second signal and obtains the address from the first signal and the second signal.
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公开(公告)号：US20220291871A1
公开(公告)日：2022-09-15
申请号：US17828176
申请日：2022-05-31
Applicant: Samsung Electronics Co., Ltd.
Inventor： SEONKYOO LEE , JEONGDON IHM , CHIWEON YOON , BYUNGHOON JEONG
Abstract: A nonvolatile memory device includes a first pin that receives a first signal, a second pin that receives a second signal, third pins that receive third signals, a fourth pin that receives a write enable signal, a memory cell array, and a memory interface circuit that obtains a command, an address, and data from the third signals in a first mode and obtains the command and the address from the first signal and the second signal and the data from the third signals in a second mode. In the first mode, the memory interface circuit obtains the command from the third signals and obtains the address from the third signals. In the second mode, the memory interface circuit obtains the command from the first signal and the second signal and obtains the address from the first signal and the second signal.
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Patent Agency Ranking
公开(公告)号：US20220230666A1
公开(公告)日：2022-07-21
申请号：US17404510
申请日：2021-08-17
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： TONGSUNG KIM , YOUNGMIN JO , MANJAE YANG , CHIWEON YOON , JUNHA LEE , BYUNGHOON JEONG
Abstract: A storage device includes a plurality of memory chips and a chip. The plurality of memory chips includes a first memory chip configured to generate a first signal based on a first clock signal, and a second memory chip configured to generate a second signal based on a second clock signal. The chip is configured to receive the first and second signals and generate and output a first and second comparison signal based on a duty cycle of the first and second signals. The first memory chip is further configured to generate a first corrected signal by adjusting a duty cycle of the first clock signal based on the first comparison signal, and the second memory chip is further configured to generate a second corrected signal by adjusting a duty cycle of the second clock signal based on the second comparison signal.
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公开(公告)号：US20240379141A1
公开(公告)日：2024-11-14
申请号：US18781289
申请日：2024-07-23
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： TONGSUNG KIM , YOUNGMIN JO , MANJAE YANG , CHIWEON YOON , JUNHA LEE , BYUNGHOON JEONG
Abstract: A storage device includes a plurality of memory chips and a chip. The plurality of memory chips includes a first memory chip configured to generate a first signal based on a first clock signal, and a second memory chip configured to generate a second signal based on a second clock signal. The chip is configured to receive the first and second signals and generate and output a first and second comparison signal based on a duty cycle of the first and second signals. The first memory chip is further configured to generate a first corrected signal by adjusting a duty cycle of the first clock signal based on the first comparison signal, and the second memory chip is further configured to generate a second corrected signal by adjusting a duty cycle of the second clock signal based on the second comparison signal.
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公开(公告)号：US20220101895A1
公开(公告)日：2022-03-31
申请号：US17477931
申请日：2021-09-17
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： YOUNGMIN JO , Byunghoon Jeong , TONGSUNG KIM , CHIWEON YOON , SEONKYOO LEE
IPC: G11C7/10
Abstract: A memory device includes a memory cell array, a page buffer, a control logic circuit, a plurality of input/output pins, a data bus inversion (DBI) pin, and an interface circuit. The page buffer is connected to the memory cell array. The control logic circuit is configured to control an operation of the memory cell array. The plurality of input/output pins receive a plurality of data signals from the controller. The DBI pin receives a DBI signal from the controller. The interface circuit count a first number of bits having a logic value of 1 and a second number of bits having a logic value of 0 from the data signals and the DBI signal and provide the data signals to the page buffer or the control logic circuit based on the first number and the second number.
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公开(公告)号：US20170004886A1
公开(公告)日：2017-01-05
申请号：US15085498
申请日：2016-03-30
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： DONGHUN KWAK , MYOUNG-WON YOON , DAESEOK BYEON , CHIWEON YOON
CPC classification number: G11C16/3404 , G11C16/0483 , G11C16/10 , G11C16/16 , G11C16/26 , G11C16/3459 , G11C16/349 , G11C16/3495
Abstract: A storage device includes a nonvolatile memory device including memory blocks and a controller configured to control the nonvolatile memory device. Each of the memory blocks includes a plurality of cell strings each including at least one selection transistor and a plurality of memory cells stacked on a substrate in a direction perpendicular to the substrate. The controller controls the nonvolatile memory device to perform a read operation on some of selection transistors of a selected one of the memory blocks and to perform a program operation on the selection transistors of the selected memory block according to a result of the read operation.
Abstract translation: 存储装置包括包括存储器块的非易失性存储器件和被配置为控制非易失性存储器件的控制器。 每个存储块包括多个单元串，每个单元串包括至少一个选择晶体管和沿垂直于该基板的方向堆叠在基板上的多个存储单元。 控制器控制非易失性存储器件对所选存储块中的一些选择晶体管执行读操作，并根据读操作的结果对所选存储块的选择晶体管执行编程操作。
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公开(公告)号：US20240393981A1
公开(公告)日：2024-11-28
申请号：US18793984
申请日：2024-08-05
Applicant: Samsung Electronics Co., Ltd.
Inventor： SEONKYOO LEE , JEONGDON IHM , CHIWEON YOON , BYUNGHOON JEONG
Abstract: A nonvolatile memory device includes a first pin that receives a first signal, a second pin that receives a second signal, third pins that receive third signals, a fourth pin that receives a write enable signal, a memory cell array, and a memory interface circuit that obtains a command, an address, and data from the third signals in a first mode and obtains the command and the address from the first signal and the second signal and the data from the third signals in a second mode. In the first mode, the memory interface circuit obtains the command from the third signals and obtains the address from the third signals. In the second mode, the memory interface circuit obtains the command from the first signal and the second signal and obtains the address from the first signal and the second signal.
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