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    NONVOLATILE MEMORY DEVICE SUPPORTING HIGH-EFFICIENCY I/O INTERFACE
    3.
    发明申请
    NONVOLATILE MEMORY DEVICE SUPPORTING HIGH-EFFICIENCY I/O INTERFACE 有权

    公开(公告)号：US20220291871A1

    公开(公告)日：2022-09-15

    申请号：US17828176

    申请日：2022-05-31

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： SEONKYOO LEE ,  JEONGDON IHM ,  CHIWEON YOON ,  BYUNGHOON JEONG

    IPC: G06F3/06 ,  G11C16/26 ,  G06F1/06 ,  G11C16/04 ,  G11C16/10 ,  G06F13/16

    Abstract: A nonvolatile memory device includes a first pin that receives a first signal, a second pin that receives a second signal, third pins that receive third signals, a fourth pin that receives a write enable signal, a memory cell array, and a memory interface circuit that obtains a command, an address, and data from the third signals in a first mode and obtains the command and the address from the first signal and the second signal and the data from the third signals in a second mode. In the first mode, the memory interface circuit obtains the command from the third signals and obtains the address from the third signals. In the second mode, the memory interface circuit obtains the command from the first signal and the second signal and obtains the address from the first signal and the second signal.

    NONVOLATILE MEMORY DEVICE SUPPORTING HIGH-EFFICIENCY I/O INTERFACE
    4.
    发明申请
    NONVOLATILE MEMORY DEVICE SUPPORTING HIGH-EFFICIENCY I/O INTERFACE 有权

    公开(公告)号：US20240393981A1

    公开(公告)日：2024-11-28

    申请号：US18793984

    申请日：2024-08-05

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： SEONKYOO LEE ,  JEONGDON IHM ,  CHIWEON YOON ,  BYUNGHOON JEONG

    IPC: G06F3/06 ,  G06F1/06 ,  G06F13/16 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26

    Abstract: A nonvolatile memory device includes a first pin that receives a first signal, a second pin that receives a second signal, third pins that receive third signals, a fourth pin that receives a write enable signal, a memory cell array, and a memory interface circuit that obtains a command, an address, and data from the third signals in a first mode and obtains the command and the address from the first signal and the second signal and the data from the third signals in a second mode. In the first mode, the memory interface circuit obtains the command from the third signals and obtains the address from the third signals. In the second mode, the memory interface circuit obtains the command from the first signal and the second signal and obtains the address from the first signal and the second signal.

    NONVOLATILE MEMORY DEVICE SUPPORTING HIGH-EFFICIENCY I/O INTERFACE
    5.
    发明申请
    NONVOLATILE MEMORY DEVICE SUPPORTING HIGH-EFFICIENCY I/O INTERFACE 有权

    公开(公告)号：US20220011974A1

    公开(公告)日：2022-01-13

    申请号：US17168620

    申请日：2021-02-05

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： SEONKYOO LEE ,  JEONGDON IHM ,  CHIWEON YOON ,  BYUNGHOON JEONG

    IPC: G06F3/06 ,  G06F13/16 ,  G06F1/06 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26

    Abstract: A nonvolatile memory device includes a first pin that receives a first signal, a second pin that receives a second signal, third pins that receive third signals, a fourth pin that receives a write enable signal, a memory cell array, and a memory interface circuit that obtains a command, an address, and data from the third signals in a first mode and obtains the command and the address from the first signal and the second signal and the data from the third signals in a second mode. In the first mode, the memory interface circuit obtains the command from the third signals and obtains the address from the third signals. In the second mode, the memory interface circuit obtains the command from the first signal and the second signal and obtains the address from the first signal and the second signal.

    METHOD OF SHAPING A STROBE SIGNAL, A DATA STORAGE SYSTEM AND STROBE SIGNAL SHAPING DEVICE
    6.
    发明申请
    METHOD OF SHAPING A STROBE SIGNAL, A DATA STORAGE SYSTEM AND STROBE SIGNAL SHAPING DEVICE 有权
    形成行走信号的方法，数据存储系统和结构信号形成装置

    公开(公告)号：US20150294730A1

    公开(公告)日：2015-10-15

    申请号：US14600353

    申请日：2015-01-20

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： JANGWOO LEE ,  KYOUNGTAE KANG ,  TAESUNG LEE ,  JEONGDON IHM

    IPC: G11C16/32

    CPC classification number: G11C16/26 ,  G11C16/30 ,  G11C16/32

    Abstract: A strobe signal shaping method for a data storage system includes receiving a strobe signal; boosting a first clock edge portion of the strobe signal when the strobe signal is received after having been idle or paused over a predetermined time period; and returning to an operating mode in which boosting is turned off with respect to a second clock edge portion of the strobe signal.

    Abstract translation: 数据存储系统的选通信号整形方法包括接收选通信号; 当在预定时间段内空闲或暂停之后接收到选通信号时，提升选通信号的第一时钟边缘部分; 并且返回到相对于选通信号的第二时钟边缘部分关闭升压的操作模式。

    SEMICONDUCTOR MEMORY DEVICE INCLUDING VERTICAL CELL TRANSISTORS
    7.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE INCLUDING VERTICAL CELL TRANSISTORS 有权

    公开(公告)号：US20250159873A1

    公开(公告)日：2025-05-15

    申请号：US18747036

    申请日：2024-06-18

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： YOUNG SEOK PARK ,  HYUN-CHUL YOON ,  ChangSik YOO ,  JEONGDON IHM

    IPC: H10B12/00

    Abstract: A semiconductor memory device includes a peripheral circuit structure, and a cell array structure provided thereon and including a plurality of cell array regions and an upper peripheral region provided between a plurality of cell array regions. A cell array structure includes vertical cell transistors, first vertical peripheral transistors, and second vertical peripheral transistors. Each of vertical cell transistors, a first vertical peripheral transistors, and a second vertical peripheral transistors has a channel extending along a third direction parallel to an arrangement direction of a peripheral circuit structure and a cell array structure. Vertical cell transistors are disposed in a cell array region and have a first polarity. First vertical peripheral transistors are disposed in an upper peripheral region and have a first polarity. Second vertical peripheral transistors are disposed in an upper peripheral region and have a second polarity different from a first polarity.

    STORAGE DEVICE AND RETRAINING METHOD THEREOF
    8.
    发明申请
    STORAGE DEVICE AND RETRAINING METHOD THEREOF 有权

    公开(公告)号：US20210349660A1

    公开(公告)日：2021-11-11

    申请号：US17030635

    申请日：2020-09-24

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： TONGSUNG KIM ,  JANGWOO LEE ,  SEONKYOO LEE ,  CHIWEON YOON ,  JEONGDON IHM

    IPC: G06F3/06 ,  G06K9/62

    Abstract: A storage device includes NVM package and a controller connected to the NVM package through a channel and controlling operation of the NVM package. The NVM package includes an interface chip, first NVM devices connected to the interface chip through a first internal channel and second NVM devices connected to the interface chip through a second internal channel. The interface chip selects the first internal channel in response to an operation request received from the controller and connects the first internal channel to the channel. The interface chip also determines whether retraining is necessary in relation to the second internal channel and transmits a retraining request to the controller when retraining is necessary.

    SEMICONDUCTOR MEMORY SYSTEM, SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SEMICONDUCTOR MEMORY DEVICE
    9.
    发明申请
    SEMICONDUCTOR MEMORY SYSTEM, SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SEMICONDUCTOR MEMORY DEVICE 有权
    半导体存储器系统，半导体存储器件和操作半导体存储器件的方法

    公开(公告)号：US20170053683A1

    公开(公告)日：2017-02-23

    申请号：US15198564

    申请日：2016-06-30

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： SEONKYOO LEE ,  TAESUNG LEE ,  JEONGDON IHM ,  BYUNGHOON JEONG

    IPC: G11C7/22 ,  G11C7/10

    CPC classification number: G11C7/22 ,  G06F11/10 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1087 ,  G11C7/1093 ,  G11C16/32

    Abstract: A semiconductor device of the inventive concept includes a timing circuit configured to receive a first timing signal of a first pulse width from an external device and output a second timing signal having a pulse width which is gradually being reduced from a second pulse width longer than the pulse width of the first timing signal, and a data input/output circuit receiving the second timing signal and outputting data to the external device in synchronization with the second timing signal.

    Abstract translation: 本发明构思的半导体器件包括：定时电路，被配置为从外部设备接收第一脉冲宽度的第一定时信号，并输出第二定时信号，该第二定时信号具有从第二脉冲宽度逐渐减小的脉冲宽度 第一定时信号的脉冲宽度和接收第二定时信号的数据输入/输出电路，并且与第二定时信号同步地将数据输出到外部设备。

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