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    SEMICONDUCTOR MEMORY SYSTEM, SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SEMICONDUCTOR MEMORY DEVICE
    2.
    发明申请
    SEMICONDUCTOR MEMORY SYSTEM, SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SEMICONDUCTOR MEMORY DEVICE 有权
    半导体存储器系统，半导体存储器件和操作半导体存储器件的方法

    公开(公告)号：US20170053683A1

    公开(公告)日：2017-02-23

    申请号：US15198564

    申请日：2016-06-30

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： SEONKYOO LEE ,  TAESUNG LEE ,  JEONGDON IHM ,  BYUNGHOON JEONG

    IPC: G11C7/22 ,  G11C7/10

    CPC classification number: G11C7/22 ,  G06F11/10 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1087 ,  G11C7/1093 ,  G11C16/32

    Abstract: A semiconductor device of the inventive concept includes a timing circuit configured to receive a first timing signal of a first pulse width from an external device and output a second timing signal having a pulse width which is gradually being reduced from a second pulse width longer than the pulse width of the first timing signal, and a data input/output circuit receiving the second timing signal and outputting data to the external device in synchronization with the second timing signal.

    Abstract translation: 本发明构思的半导体器件包括：定时电路，被配置为从外部设备接收第一脉冲宽度的第一定时信号，并输出第二定时信号，该第二定时信号具有从第二脉冲宽度逐渐减小的脉冲宽度 第一定时信号的脉冲宽度和接收第二定时信号的数据输入/输出电路，并且与第二定时信号同步地将数据输出到外部设备。

    NONVOLATILE MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME
    3.
    发明申请
    NONVOLATILE MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME 有权
    非易失性存储器件和包括其的存储器系统

    公开(公告)号：US20150287475A1

    公开(公告)日：2015-10-08

    申请号：US14546039

    申请日：2014-11-18

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： SUNGJUN KIM ,  SANGTAE KIM ,  BYUNGHOON JEONG

    IPC: G11C17/18 ,  G11C17/16

    CPC classification number: G11C17/18 ,  G11C13/0007 ,  G11C13/004 ,  G11C17/16 ,  G11C17/165 ,  G11C29/78 ,  G11C2013/0042 ,  G11C2213/71 ,  G11C2213/72

    Abstract: A nonvolatile memory device is provided. The nonvolatile memory device includes a memory cell array, an anti-fuse cell array, a sense amplifier, a page buffer, and a control logic. The memory cell array includes memory cells connected to word lines and bit lines. The anti-fuse cell array stores setting information for controlling the memory cell array. The anti-fuse cell array includes anti-fuse cells connected to the bit lines. The sense amplifier is connected to the bit lines to sense the memory cells or the anti-fuse cells. The page buffer stores data that is read out from the memory cells or the anti-fuse cells. The control logic controls the sense amplifiers and the page buffer to read out data from the memory cell array or the anti-fuse cell array.

    Abstract translation: 提供非易失性存储器件。 非易失性存储器件包括存储单元阵列，反熔丝单元阵列，读出放大器，页面缓冲器和控制逻辑。 存储单元阵列包括连接到字线和位线的存储单元。 反熔丝单元阵列存储用于控制存储单元阵列的设置信息。 反熔丝单元阵列包括连接到位线的反熔丝单元。 读出放大器连接到位线以感测存储单元或反熔丝单元。 页面缓冲器存储从存储单元或反熔丝单元读出的数据。 控制逻辑控制读出放大器和页缓冲器从存储单元阵列或反熔丝单元阵列中读出数据。

    NONVOLATILE MEMORY DEVICE SUPPORTING HIGH-EFFICIENCY I/O INTERFACE
    4.
    发明申请
    NONVOLATILE MEMORY DEVICE SUPPORTING HIGH-EFFICIENCY I/O INTERFACE 有权

    公开(公告)号：US20240393981A1

    公开(公告)日：2024-11-28

    申请号：US18793984

    申请日：2024-08-05

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： SEONKYOO LEE ,  JEONGDON IHM ,  CHIWEON YOON ,  BYUNGHOON JEONG

    IPC: G06F3/06 ,  G06F1/06 ,  G06F13/16 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26

    Abstract: A nonvolatile memory device includes a first pin that receives a first signal, a second pin that receives a second signal, third pins that receive third signals, a fourth pin that receives a write enable signal, a memory cell array, and a memory interface circuit that obtains a command, an address, and data from the third signals in a first mode and obtains the command and the address from the first signal and the second signal and the data from the third signals in a second mode. In the first mode, the memory interface circuit obtains the command from the third signals and obtains the address from the third signals. In the second mode, the memory interface circuit obtains the command from the first signal and the second signal and obtains the address from the first signal and the second signal.

    NONVOLATILE MEMORY DEVICE SUPPORTING HIGH-EFFICIENCY I/O INTERFACE
    6.
    发明申请
    NONVOLATILE MEMORY DEVICE SUPPORTING HIGH-EFFICIENCY I/O INTERFACE 有权

    公开(公告)号：US20220011974A1

    公开(公告)日：2022-01-13

    申请号：US17168620

    申请日：2021-02-05

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： SEONKYOO LEE ,  JEONGDON IHM ,  CHIWEON YOON ,  BYUNGHOON JEONG

    IPC: G06F3/06 ,  G06F13/16 ,  G06F1/06 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26

    Abstract: A nonvolatile memory device includes a first pin that receives a first signal, a second pin that receives a second signal, third pins that receive third signals, a fourth pin that receives a write enable signal, a memory cell array, and a memory interface circuit that obtains a command, an address, and data from the third signals in a first mode and obtains the command and the address from the first signal and the second signal and the data from the third signals in a second mode. In the first mode, the memory interface circuit obtains the command from the third signals and obtains the address from the third signals. In the second mode, the memory interface circuit obtains the command from the first signal and the second signal and obtains the address from the first signal and the second signal.

    NONVOLATILE MEMORY DEVICE SUPPORTING HIGH-EFFICIENCY I/O INTERFACE
    8.
    发明申请
    NONVOLATILE MEMORY DEVICE SUPPORTING HIGH-EFFICIENCY I/O INTERFACE 有权

    公开(公告)号：US20220291871A1

    公开(公告)日：2022-09-15

    申请号：US17828176

    申请日：2022-05-31

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： SEONKYOO LEE ,  JEONGDON IHM ,  CHIWEON YOON ,  BYUNGHOON JEONG

    IPC: G06F3/06 ,  G11C16/26 ,  G06F1/06 ,  G11C16/04 ,  G11C16/10 ,  G06F13/16

    Abstract: A nonvolatile memory device includes a first pin that receives a first signal, a second pin that receives a second signal, third pins that receive third signals, a fourth pin that receives a write enable signal, a memory cell array, and a memory interface circuit that obtains a command, an address, and data from the third signals in a first mode and obtains the command and the address from the first signal and the second signal and the data from the third signals in a second mode. In the first mode, the memory interface circuit obtains the command from the third signals and obtains the address from the third signals. In the second mode, the memory interface circuit obtains the command from the first signal and the second signal and obtains the address from the first signal and the second signal.

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