公开(公告)号：US20230154527A1

公开(公告)日：2023-05-18

申请号：US17852035

申请日：2022-06-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： EUNJIN SONG ,  KYOUNGTAE KANG ,  SANGLOK KIM ,  CHIWEON YOON ,  BYUNGHOON JEONG

IPC: G11C11/4096 ,  G11C11/4093 ,  G11C11/4074 ,  G11C11/4094

CPC classification number: G11C11/4096 ,  G11C11/4093 ,  G11C11/4074 ,  G11C11/4094

Abstract: A data transfer circuit in a nonvolatile memory device includes first repeaters, second repeaters and signal lines. The signal lines connect the first repeaters and the second repeaters, and include a first group of signal lines and a second group of signal lines alternatingly arranged. The first repeaters include a first group of repeaters activated in a first operation mode and a second group of repeaters activated in a second operation mode. The second repeaters include a third group of repeaters activated in the first operation mode and are connected to the first group of repeaters through the first group of signal lines floated in the second operation mode, and a fourth group of repeaters activated in the second operation mode and are connected to the second group of repeaters through the second group of signal lines floated in the first operation mode.

公开(公告)号：US20220076778A1

公开(公告)日：2022-03-10

申请号：US17239651

申请日：2021-04-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SANGLOK KIM ,  YOUNGDON CHOI

IPC: G11C29/56

Abstract: A semiconductor memory device included in each of a plurality of chips which are divided by a scribe lane and formed on an upper surface of a wafer, includes a memory core and a built-in self test (BIST) circuit. The memory core includes a memory cell array that stores data and a data input/output circuit connected to a data input/output pad. The BIST circuit is connected to a test pad that is separate from the data input/output pad. The BIST circuit generates test pattern data including first parallel bits based on commands and addresses received from an external automatic test equipment (ATE) during a wafer level test process performed on the semiconductor memory device. The BIST circuit tests the memory core by applying the test pattern data to the memory cell array through the data input/output circuit.