公开(公告)号：US20250159873A1

公开(公告)日：2025-05-15

申请号：US18747036

申请日：2024-06-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YOUNG SEOK PARK ,  HYUN-CHUL YOON ,  ChangSik YOO ,  JEONGDON IHM

IPC: H10B12/00

Abstract: A semiconductor memory device includes a peripheral circuit structure, and a cell array structure provided thereon and including a plurality of cell array regions and an upper peripheral region provided between a plurality of cell array regions. A cell array structure includes vertical cell transistors, first vertical peripheral transistors, and second vertical peripheral transistors. Each of vertical cell transistors, a first vertical peripheral transistors, and a second vertical peripheral transistors has a channel extending along a third direction parallel to an arrangement direction of a peripheral circuit structure and a cell array structure. Vertical cell transistors are disposed in a cell array region and have a first polarity. First vertical peripheral transistors are disposed in an upper peripheral region and have a first polarity. Second vertical peripheral transistors are disposed in an upper peripheral region and have a second polarity different from a first polarity.